IN16C1054
7.9 Modem Status Register (MSR, Page 0)
MSR provides the current status of control signals from modem or auxiliary devices.
MSR[3:0] are set to ‘1’ when input from modem changes and cleared to ‘0’ as soon as
CPU reads MSR. Table 15 shows MSR bit settings.
Table 15: Modem Status Register Description
Bit
7
Symbol
MSR[7]
Description
DCD Input Status.
Complement of Data Carrier Detect (DCD#) input.
In loop back mode this bit is equivalent to OUT2 in the MCR.
RI Input Status.
6
5
4
3
2
1
0
MSR[6]
MSR[5]
MSR[4]
MSR[3]
MSR[2]
MSR[1]
MSR[0]
Complement of Ring Indicator (RI#) input.
In loop back mode this bit is equivalent to OUT1 in the MCR.
DSR Input Status.
Complement of Data Set Ready (DSR#) input.
In loop back mode this bit is equivalent to DTR in the MCR.
CTS Input Status.
Complement of Clear To Send (CTS#) input.
In loop back mode this bit is equivalent to RTS in the MCR.
∆DCD Input Status.
0 : No change on CD# input (default).
1 : Indicates that the DCD# input has changed state.
∆RI Input Status.
0 : No change on RI# input (default).
1 : Indicates that the RI# input has changed state from ‘0’ to ‘1’.
∆DSR Input Status.
0 : No change on DSR# input (deault).
1 : Indicates that the DSR# input has changed state.
∆CTS Input Status.
0 : No change on CTS# input (deault).
1 : Indicates that the CTS# input has changed state.
7.10 Scratch Pad Register (SPR, Page 0)
This 8-bit Read/Write Register does not control the UART in anyway. It is intended as a
scratch pad register to be used by the programmer to hold data temporarily.
7.11 Divisor Latches (DLL, DLH, Page 1)
Two 8-bit registers which store the 16-bit divisor for generation of the clock in baud rate
generator. DLH stores the most significant part of the divisor, and DLL stores the least
significant part of the divisor. Divisor of zero is not recommended.
Note that DLL and DLH can only be written to before sleep mode is enabled, i.e., before
IER[4] is set. Chapter 6.7 describes the details of divisor latches.
Rev. 00
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