IDT72T7285/72T7295/72T72105/72T72115 2.5V TeraSync
16,384 x 72, 32,768 x 72, 65,536 x 72, 131,072 x 72
72-BIT FIFO
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
tCLKH
tCLKL
WCLK
tENS
tENH
WEN
PAF
tPAFA
D - m words
in FIFO
D - (m + 1) words
in FIFO
D - (m + 1) words in FIFO
tPAFA
RCLK
tENS
REN
5994 drw30
NOTES:
1. m = PAF offset.
2. D = maximum FIFO Depth.
In IDT Standard Mode: D= 16,384 for the IDT72T7285, 32,768 for the IDT72T7295, 65,536 for the IDT72T72105 and 131,072 for the IDT72T72115.
In FWFT Mode: D= 16,385 for the IDT72T7285, 32,769 for the IDT72T7295, 65,537 for the IDT72T72105 and 131,073 for the IDT72T72115.
3. PAF is asserted to LOW on WCLK transition and reset to HIGH on RCLK transition.
4. Select this mode by setting PFM LOW during Master Reset.
5. RCS = LOW.
Figure 25. Asynchronous Programmable Almost-Full Flag Timing (IDT Standard and FWFT Modes)
tCLKH
tCLKL
WCLK
tENS
tENH
WEN
tPAEA
(2)
(2)
n words in FIFO
,
n words in FIFO
,
(2)
n + 1 words in FIFO
n + 2 words in FIFO
,
(3)
PAE
RCLK
REN
(3)
n + 1 words in FIFO
n + 1 words in FIFO
(3)
tPAEA
tENS
5994 drw31
NOTES:
1. n = PAE offset.
2. For IDT Standard Mode.
3. For FWFT Mode.
4. PAE is asserted LOW on RCLK transition and reset to HIGH on WCLK transition.
5. Select this mode by setting PFM LOW during Master Reset.
6. RCS = LOW.
Figure 26. Asynchronous Programmable Almost-Empty Flag Timing (IDT Standard and FWFT Modes)
44
IDT [ INTEGRATED DEVICE TECHNOLOGY ]
