IDT72T7285/72T7295/72T72105/72T72115 2.5V TeraSync
16,384 x 72, 32,768 x 72, 65,536 x 72, 131,072 x 72
72-BIT FIFO
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
tCLKL
tCLKL
WCLK
WEN
PAF
1
2
2
1
t
ENS
tENH
t
PAFS
tPAFS
D - m words in FIFO(2)
D-(m+1) words
in FIFO(2)
D - (m +1) words in FIFO(2)
t
SKEW2(3)
RCLK
tENH
t
ENS
5994 drw28
REN
NOTES:
1. m = PAF offset.
2. D = maximum FIFO depth.
In IDT Standard mode: D = 16,384 for the IDT72T7285, 32,768 for the IDT72T7295, 65,536 for the IDT72T72105 and 131,072 for the IDT72T72115.
In FWFT mode: D = 16,385 for the IDT72T7285, 32,769 for the IDT72T7295, 65,537 for the IDT72T72105 and 131,073 for the IDT72T72115.
3. tSKEW2 is the minimum time between a rising RCLK edge and a rising WCLK edge to guarantee that PAF will go HIGH (after one WCLK cycle plus tPAFS). If the time between the
rising edge of RCLK and the rising edge of WCLK is less than tSKEW2, then the PAF deassertion time may be delayed one extra WCLK cycle.
4. PAF is asserted and updated on the rising edge of WCLK only.
5. Select this mode by setting PFM HIGH during Master Reset.
Figure 23. Synchronous Programmable Almost-Full Flag Timing (IDT Standard and FWFT Modes)
tCLKH
tCLKL
WCLK
t
ENS
tENH
WEN
PAE
n words in FIFO(2)
n + 1 words in FIFO(3)
,
n words in FIFO(2)
n + 1 words in FIFO(3)
,
n + 1 words in FIFO(2)
n + 2 words in FIFO(3)
,
SKEW2(4)
t
PAES
t
PAES
t
1
2
1
2
RCLK
REN
t
ENS
tENH
5994 drw29
NOTES:
1. n = PAE offset.
2. For IDT Standard mode
3. For FWFT mode.
4. tSKEW2 is the minimum time between a rising WCLK edge and a rising RCLK edge to guarantee that PAE will go HIGH (after one RCLK cycle plus tPAES). If the time between the
rising edge of WCLK and the rising edge of RCLK is less than tSKEW2, then the PAE deassertion may be delayed one extra RCLK cycle.
5. PAE is asserted and updated on the rising edge of WCLK only.
6. Select this mode by setting PFM HIGH during Master Reset.
7. RCS = LOW.
Figure 24. Synchronous Programmable Almost-Empty Flag Timing (IDT Standard and FWFT Modes)
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