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IDT7005S35JB 参数 Datasheet PDF下载

IDT7005S35JB图片预览
型号: IDT7005S35JB
PDF下载: 下载PDF文件 查看货源
内容描述: 高速8K ×8双端口静态RAM [HIGH-SPEED 8K x 8 DUAL-PORT STATIC RAM]
分类和应用:
文件页数/大小: 20 页 / 265 K
品牌: IDT [ INTEGRATED DEVICE TECHNOLOGY ]
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IDT7005S/L  
HIGH-SPEED 8K x 8 DUAL-PORT STATIC RAM  
MILITARY AND COMMERCIAL TEMPERATURE RANGES  
AC ELECTRICAL CHARACTERISTICS OVER THE  
OPERATING TEMPERATURE AND SUPPLY VOLTAGE (5)  
IDT7005X15  
Com'l. Only  
IDT7005X17  
Com'l. Only  
IDT7005X20  
IDT7005X25  
Symbol  
Parameter  
Min.  
Max.  
Min.  
Max.  
Min.  
Max.  
Min.  
Max. Unit  
WRITE CYCLE  
tWC  
tEW  
tAW  
tAS  
Write Cycle Time  
Chip Enable to End-of-Write(3)  
15  
12  
12  
0
10  
10  
17  
12  
12  
0
10  
10  
20  
15  
15  
0
12  
12  
25  
20  
20  
0
15  
15  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
Address Valid to End-of-Write  
Address Set-up Time(3)  
tWP  
tWR  
tDW  
tHZ  
Write Pulse Width  
12  
0
12  
0
15  
0
20  
0
Write Recovery Time  
Data Valid to End-of-Write  
Output High-Z Time(1, 2)  
Data Hold Time(4)  
Write Enable to Output in High-Z(1, 2)  
Output Active from End-of-Write(1, 2, 4)  
SEM Flag Write to Read Time  
SEM Flag Contention Window  
10  
0
10  
0
15  
0
15  
0
tDH  
tWZ  
tOW  
tSWRD  
tSPS  
0
0
0
0
5
5
5
5
5
5
5
5
IDT7005X35  
IDT7005X55  
IDT7005X70  
Mil. Only  
Symbol  
Parameter  
Min.  
Max.  
Min.  
Max.  
Min.  
Max. Unit  
WRITE CYCLE  
tWC  
tEW  
Write Cycle Time  
35  
30  
30  
0
15  
15  
55  
45  
45  
0
25  
25  
70  
50  
50  
0
30  
30  
ns  
ns  
Chip Enable to End-of-Write(3)  
Address Valid to End-of-Write  
Address Set-up Time(3)  
tAW  
ns  
tAS  
ns  
tWP  
Write Pulse Width  
25  
0
40  
0
50  
0
ns  
tWR  
Write Recovery Time  
ns  
tDW  
Data Valid to End-of-Write  
Output High-Z Time(1, 2)  
Data Hold Time(4)  
Write Enable to Output in High-Z(1, 2)  
Output Active from End-of-Write(1, 2, 4)  
SEM Flag Write to Read Time  
SEM Flag Contention Window  
15  
0
30  
0
40  
0
ns  
tHZ  
ns  
tDH  
ns  
tWZ  
0
0
0
ns  
tOW  
ns  
tSWRD  
tSPS  
NOTES:  
5
5
5
ns  
5
5
5
ns  
2738 tbl 14  
1. Transition is measured ±500mV from Low or High-impedance voltage with the Output Test Load (Figure 2).  
2. This parameter is guaranteed by device characterization but is not production tested.  
3. To access RAM, CE = VIL, SEM = VIH. To access semaphore, CE = VIH and SEM = VIL. Either condition must be valid for the entire tEW time.  
4. The specification for tDH must be met by the device supplying write data to the RAM under all operating conditions. Although tDH and tOW values will vary  
over voltage and temperature, the actual tDH will always be smaller than the actual tOW.  
5. "X" in part numbers indicates power rating (S or L).  
6.06  
9