IDT7005S/L
HIGH-SPEED 8K x 8 DUAL-PORT STATIC RAM
MILITARY AND COMMERCIAL TEMPERATURE RANGES
TIMING WAVEFORM OF SEMAPHORE READ AFTER WRITE TIMING, EITHER SIDE(1)
t
OH
t
SAA
A0-A2
VALID ADDRESS
VALID ADDRESS
t
WR
t
ACE
t
AW
tEW
SEM
t
SOP
t
DW
DATAIN
VALID
DATAOUT
I/O
(2)
VALID
t
AS
t
WP
t
DH
R/W
t
SWRD
tAOE
OE
Write Cycle
Read Cycle
2738 drw 11
NOTES:
1. CE = VIH for the duration of the above timing (both write and read cycle).
2. "DATAOUT VALID" represents all I/O's (I/O0-I/O7) equal to the semaphore value.
TIMING WAVEFORM OF SEMAPHORE WRITE CONTENTION(1,3,4)
A
0"A"-A2"A"
MATCH
SIDE(2) “A”
R/W"A"
SEM"A"
tSPS
A
0"B"-A2"B"
MATCH
SIDE(2)
“B”
R/W"B"
SEM"B"
2738 drw 12
NOTES:
1. DOR = DOL = VIL, CER = CEL = VIH. Semaphore flag is released from both sides (reads as ones from both sides) at cycle start.
2. All timing is the same for left and right ports. Port “A” may be either left or right port. “B” is the opposite from port “A”.
3. This parameter is measured from R/W"A" or SEM"A" going High to R/W"B" or SEM"B" going High.
4. If tSPS is not satisfied, the semaphore will fall positively to one side or the other, but there is no guarantee which side will be granted the semaphore flag.
6.06
11
IDT [ INTEGRATED DEVICE TECHNOLOGY ]
