IDT7005S/L
HIGH-SPEED 8K x 8 DUAL-PORT STATIC RAM
MILITARY AND COMMERCIAL TEMPERATURE RANGES
AC ELECTRICAL CHARACTERISTICS OVER THE
OPERATING TEMPERATURE AND SUPPLY VOLTAGE RANGE(6)
IDT7005X15 IDT7005X17
Com'l. Only Com'l. Only
IDT7005X20
IDT7005X25
Symbol
Parameter
Min. Max. Min. Max.
Min.
Max.
Min.
Max. Unit
BUSY TIMING (M/S = VIH)
tBAA
tBDA
tBAC
tBDC
tAPS
tBDD
tWH
BUSY Access Time from Address Match
BUSY Disable Time from Address Not Matched
BUSY Access Time from Chip Enable Low
BUSY Disable Time from Chip Enable High
Arbitration Priority Set-up Time(2)
BUSY Disable to Valid Data(3)
Write Hold After BUSY(5)
—
—
—
—
5
15
15
15
15
—
18
—
—
—
—
—
5
17
17
17
17
—
18
—
—
—
—
—
5
20
20
20
17
—
30
—
—
—
—
—
5
20
20
20
17
—
30
—
ns
ns
ns
ns
ns
ns
ns
—
—
13
—
15
—
17
12
BUSY TIMING (M/S = VIL)
tWB
tWH
BUSY Input to Write(4)
Write Hold After BUSY(5)
0
—
—
0
—
—
0
—
—
0
—
—
ns
ns
12
13
15
17
PORT-TO-PORT DELAY TIMING
tWDD
tDDD
Write Pulse to Data Delay(1)
Write Data Valid to Read Data Delay(1)
—
—
30
25
—
—
30
25
—
—
45
35
—
—
50
35
ns
ns
IDT7005X35
IDT7005X55
IDT7005X70
Mil. Only
Symbol
Parameter
Min.
Max.
Min.
Max.
Min.
Max. Unit
BUSY TIMING (M/S = VIH)
tBAA
tBDA
tBAC
tBDC
tAPS
tBDD
BUSY Access Time from Address Match
—
—
—
—
5
20
20
20
20
—
35
—
—
—
—
5
45
40
40
35
—
40
—
—
—
—
5
45
40
40
35
—
45
ns
ns
ns
ns
ns
ns
BUSY Disable Time from Address Not Matched
BUSY Access Time from Chip Enable Low
BUSY Disable Time from Chip Enable High
Arbitration Priority Set-up Time(2)
BUSY Disable to Valid Data(3)
—
—
—
tWH
Write Hold After BUSY(5)
25
—
25
—
25
—
ns
BUSY TIMING (M/S = VIL)
tWB
tWH
BUSY Input to Write(4)
Write Hold After BUSY(5)
0
—
—
0
—
—
0
—
—
ns
ns
25
25
25
PORT-TO-PORT DELAY TIMING
tWDD
Write Pulse to Data Delay(1)
Write Data Valid to Read Data Delay(1)
—
—
60
45
—
—
80
65
—
—
95
80
ns
tDDD
ns
NOTES:
2738 tbl 15
1. Port-to-port delay through RAM cells from writing port to reading port, refer to "Timing Waveform of Write with Port-to-Port Read and BUSY".
2. To ensure that the earlier of the two ports wins.
3. tBDD is a calculated parameter and is the greater of 0, tWDD – tWP (actual), or tDDD – tDW (actual).
4. To ensure that the write cycle is inhibited on port "B" during contention with port "A".
5. To ensure that a write cycle is completed on port "B" after contention on port "A".
6. "X" in part numbers indicates power rating (S or L).
6.06
12
IDT [ INTEGRATED DEVICE TECHNOLOGY ]
