IDT7005S/L
HIGH-SPEED 8K x 8 DUAL-PORT STATIC RAM
MILITARY AND COMMERCIAL TEMPERATURE RANGES
WAVEFORM OF READ CYCLES
(5)
t
RC
ADDR
t
AA (4)
t
ACE (4)
t
AOE
(4)
CE
OE
R/
W
t
LZ
(1)
t
OH
VALID DATA
(4)
DATA
OUT
t
HZ (2)
BUSY
OUT
t
BDD
(3, 4)
2738 drw 07
NOTES:
1. Timing depends on which signal is asserted last,
OE
or
CE
.
2. Timing depends on which signal is de-asserted first,
CE
or
OE.
3. t
BDD
delay is required only in cases where the opposite port is completing a write operation to the same address location. For simultaneous read operations
BUSY
has no relation to valid output data.
4. Start of valid data depends on which timing becomes effective last t
AOE
, t
ACE
, t
AA
or t
BDD
.
5.
SEM
= V
IH
.
TIMING OF POWER-UP POWER-DOWN
CE
I
CC
I
SB
2738 drw 08
t
PU
50%
t
PD
50%
6.06
8
IDT [ INTEGRATED DEVICE TECHNOLOGY ]
