ICS2509C
3.3V Phase-Lock Loop Clock Driver
ICS2509C
TSD
General Layout Precautions:
An ICS2509C is used as an example.
The same rules and methods apply.
1) Use copper flooded ground on the top signal layer
under the clock buffer The area under U1 in figure 1
on the right is an example. Every ground pin goes to a
ground via. The vias are not visible in figure 1.
2) Use power vias for power and ground. Vias 20 mil or
larger in diameter have lower high frequency
impedance. Vias for signals may be minimum drill
size.
3) Make all power and ground traces are as wide as the
via pad for lower inductance.
4) VAA for pin 23 has a low pass RC filter to decouple
the digital and analog supplies. C9-12 may be replaced
with a single low ESR (0.8 ohm or less) device with
the same total capacitance. R2 may be replaced with a
ferrite bead. The bead should have a DC resistance of
at least 0.5 ohms. 1 ohm is better. It should have an
impedance of at least 300 ohms at 100MHz. 600 ohms
at 100MHz is better.
5) Notice that ground vias are never shared.
6) All VCC pins have a decoupling capacitor. Power is
always routed from the plane connection via to the
capacitor pad to the VCC pin on the clock buffer.
7) Component R1 is located at the clock source.
8) Component C1, if used, has the effect of adding delay.
9) Component C7 , if used, has the effect of subtracting
delay. Delaying the FBIn clock will cause the output
clocks to be earlier. A more effective method is to use
the propagation time of a trace between FBOut and
FBIn.
Figure 1.
Component Values:
C1,C7= As necessary for delay
adjust
C[6:2]=.01uF
C8,C13=0.1uF
C[12:9]=4.7Uf
R1=10 ohm. Locate at driver
R2=10 ohm.
0008D—03/31/03
6
IDT™ / ICS™
3.3V Phase-Lock Loop Clock Driver
6
ICS2509C
IDT [ INTEGRATED DEVICE TECHNOLOGY ]
