Integrated
Circuit
Systems, Inc.
DATA SHEET
ICS2509C
3.3V Phase-Lock Loop Clock Driver
ICS2509C
3.3V Phase-Lock Loop Clock Driver
General Description
The
ICS2509C
is a high performance, low skew, low jitter
clock driver. It uses a phase lock loop (PLL) technology to
align, in both phase and frequency, the CLKIN signal with
the CLKOUT signal. It is specifically designed for use with
synchronous SDRAMs. The
ICS2509C
operates at 3.3V
VCC and drives up to nine clock loads.
One bank of five outputs and one bank of four outputs
provide nine low-skew, low-jitter copies of CLKIN. Output
signal duty cycles are adjusted to 50 percent, independent
of the duty cycle at CLKIN. Each bank of outputs can be
enabled or disabled separately via control (OEA and OEB)
inputs. When the OE inputs are high, the outputs align in
phase and frequency with CLKIN; when the OE inputs are
low, the outputs are disabled to the logic low state.
The
ICS2509C
does not require external RC filter
components. The loop filter for the PLL is included on-chip,
minimizing component count, board space, and cost. The
buffer mode shuts off the PLL and connects the input
directly to the output buffer. This buffer mode, the
ICS2509C
can be use as low skew fanout clock buffer device. The
ICS2509C
comes in 24 pin 173mil Thin Shrink Small-
Outline package (TSSOP) package.
Features
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Meets or exceeds PC133 registered DIMM
specification 1.1
Spread Spectrum Clock Compatible
Distributes one clock input to one bank of five and one
bank of four outputs
Separate output enable(OEA,OEB) for each output
bank
Operating frequency 25 MHz to 175 Mhz
External feedback input (FBIN) terminal is used to
synchrionize the outputs to the clock input
No external RC network required
Operates at 3.3V Vcc
Plastic 24-pin 173mil TSSOP package
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Block Diagram
FBOUT
CLKA0
CLKA1
FBIN
CLKIN
PLL
CLKA2
CLKA3
AVCC
OEA
CLKB0
CLKB1
CLKB2
CLKB3
OEB
0008D—03/31/03
Pin Configuration
AGND
VCC
CLKA0
CLKA1
CLKA2
GND
GND
CLKA3
CLKA4
VCC
OEA
FBOUT
1
2
3
4
5
6
7
8
9
10
11
12
24
23
22
21
20
19
18
17
16
15
14
13
CLKIN
AVCC
VCC
CLKB0
CLKB1
GND
GND
CLKB2
CLKB3
VCC
OEB
FBIN
CLKA4
24 Pin TSSOP
4.40 mm. Body, 0.65 mm. pitch
IDT™ / ICS™
3.3V Phase-Lock Loop Clock Driver
1
ICS2509C
ICS2509C
IDT [ INTEGRATED DEVICE TECHNOLOGY ]
