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2509CYG-T 参数 Datasheet PDF下载

2509CYG-T图片预览
型号: 2509CYG-T
PDF下载: 下载PDF文件 查看货源
内容描述: [PLL Based Clock Driver, 2509 Series, 9 True Output(s), 0 Inverted Output(s), PDSO24, 4.40 MM, 0.65 MM PITCH, PLASTIC, MO-153, TSSOP-24]
分类和应用: 驱动光电二极管逻辑集成电路
文件页数/大小: 8 页 / 251 K
品牌: IDT [ INTEGRATED DEVICE TECHNOLOGY ]
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ICS2509C
3.3V Phase-Lock Loop Clock Driver
ICS2509C
TSD
Absolute Maximum Ratings
Supply Voltage (AVCC) . . . . . . . . . . . . . . . . .
Supply Voltage (VCC) . . . . . . . . . . . . . . . . . .
Logic Inputs . . . . . . . . . . . . . . . . . . . . . . . . .
Ambient Operating Temperature . . . . . . . . . .
Storage Temperature . . . . . . . . . . . . . . . . . . .
AVCC < (V
cc
+ 0.7V)
4.3 V
GND –0.5 V to V
cc
+0.5 V
0°C to +70°C
–65°C to +150°C
Stresses above those listed under
Absolute Maximum Ratings
may cause permanent damage to the device. These
ratings are stress specifications only and functional operation of the device at these or any other conditions above those
listed in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions
for extended periods may affect product reliability.
Electrical Characteristics - OUTPUT
T
A
= 0 - 70C; V
DD
= V
DDL
= 3.3 V +/-10%; C
L
= 20 - 30 pF; R
L
= 470 Ohms (unless otherwise stated)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
V
O
= V
DD
*(0.5)
36
Output Impedance
R
DSP
V
O
= V
DD
*(0.5)
32
Output Impedance
R
DSN
I
OH
= -8 mA
2.4
2.9
Output High Voltage
V
OH
I
OL
= 8 mA
0.25
Output Low Voltage
V
OL
-26
V
OH
= 2.4 V
I
OH
Output High Current
-37
V
OH
= 2.0 V
19
25
V
OL
= 0.8 V
I
OL
Output Low Current
13
17
V
OL
= 0.55 V
1
Rise Time
T
r
V
OL
= 0.8 V, V
OH
= 2.0 V
0.5
1.4
1
Fall Time
T
f
V
OH
= 2.0 V, V
OL
= 0.8 V
0.5
1.5
1
Duty Cycle
D
t
V
T
= 1.5 V;C
L
=30 pF
45
50
at 66-100 MHz ; loaded outputs
52
1
Tcyc-cyc
Cycle to Cycle jitter
at 133 MHz ; loaded outputs
39
1
Absolute Jitter
Tjabs
10000 cycles; C
L
= 30 pF
57
1
Skew
T
sk
V
T
= 1.5 V (Window) Output to Output
80
1
Phase error
T
pe
V
T
= Vdd/2; CLKIN-FBIN
-150
40
1
3
Phase error Jitter
T
pe
V
T
= Vdd/2; CLKIN-FBIN; Delay Jitter
-50
35
1
Delay Input-Output
D
R1
V
T
= 1.5 V; PLL_EN = 0
3.3
1
MAX UNITS
V
0.4
V
-13.6
mA
-22
mA
2.1
2.7
55
100
75
150
150
50
3.7
ns
ns
%
ps
ps
ps
ps
ps
ns
Guaranteed by design, not 100% tested in production.
0008D—03/31/03
3
IDT™ / ICS™
3.3V Phase-Lock Loop Clock Driver
3
ICS2509C