ICS2509C
3.3V Phase-Lock Loop Clock Driver
ICS2509C
TSD
Pin Descriptions
PIN NUM BER
1
2, 10, 15
3
4
5
6, 7, 18, 19
8
9
11
12
13
14
16
17
20
21
22
23
24
PIN NAM E
AGND
VCC
CLKA0
CLKA1
CLKA2
GND
CLKA3
CLKA4
OEA
1
FBOUT
FBIN
OEB
1
CLKB3
CLKB2
CLKB1
CLKB0
VCC
AVCC
CLKIN
TYPE
PWR
PWR
OUT
OUT
OUT
PWR
OUT
OUT
IN
OUT
IN
IN
OUT
OUT
OUT
OUT
PWR
IN
IN
DESCRIPTION
Analog Ground
Power Supply (3.3V)
Buffered clock output, Bank
Buffered clock output, Bank
Buffered clock output, Bank
Ground
Buffered clock output, Bank
Buffered clock output, Bank
A
A
A
A
A
Output enable (has internal pull_up). When high, normal operation.
When low bank A clock outputs are disabled to a logic low state.
Feedback output
Feedback input
Output enable (has internal pull_up). When high, normal operation.
When low bank B clock outputs are disabled to a logic low state.
Buffered clock output. Bank B
Buffered clock output. Bank B
Buffered clock output. Bank B
Buffered clock output. Bank B
Power Supply (3.3V) digital supply.
Analog power supply (3.3V). When input is ground PLL is off and
bypassed.
Clock input
Note:
1. Weak pull-ups on these inputs
Functionality
INPUTS
OEA
0
0
1
1
OEB
0
1
0
1
AVCC
3.33
3.33
3.33
3.33
CLKA
(0:4)
0
0
Driven
Driven
OUTPUTS
CLKB
FBOUT
(0:3)
0
Driven
Driven
Driven
0
Driven
Driven
Driven
Source
PLL
PLL
PLL
PLL
PLL
Shutdown
N
N
N
N
0
0
0
Driven
CLKIN
Y
0
1
0
Driven
CLKIN
Y
1
0
0
Driven
CLKIN
Y
1
1
0
Driven
CLKIN
Y
Test mode:
When AVCC is 0, shuts off the PLL and connects the input directly to the output buffers
0008D—03/31/03
Buffer M ode
0
0
0
Driven
Driven
0
Driven
Driven
2
IDT™ / ICS™
3.3V Phase-Lock Loop Clock Driver
2
ICS2509C
IDT [ INTEGRATED DEVICE TECHNOLOGY ]
