ICS1893CF Data Sheet Rev. J - Release
Chapter 7 Management Register Set
7.2.2 Loopback Enable (bit 0.14)
This bit controls the Loopback mode for the ICS1893CF. Setting this bit to logic:
• Zero disables the Loopback mode.
• One enables the Loopback mode by disabling the Twisted-Pair Transmitter, the Twisted-Pair Receiver,
and the collision detection circuitry. (The STA can override the ICS1893CF from disabling the collision
detection circuitry in Loopback mode by writing logic one to bit 0.7.) When the ICS1893CF is in
Loopback mode, the data presented at the MAC transmit interface is internally looped back to the MAC
receive interface. The delay from the assertion of Transmit Data Enable (TXEN) to the assertion of
Receive Data valid (RXDV) is less than 512 bit times.
7.2.3 Data Rate Select (bit 0.13)
This bit provides a means of controlling the ICS1893CF data rate. Its operation depends on the state of
several other functions, including the HW/SW input pin and the Auto-Negotiation Enable bit (bit 0.12).
When the ICS1893CF is configured for:
• Hardware mode (that is, the HW/SW pin is logic zero), the ICS1893CF isolates this bit 0.13 and uses the
10/100SEL input pin to establish the data rate for the ICS1893CF. In this Hardware mode:
– Bit 0.13 is undefined.
– The ICS1893CF provides a Data Rate Status bit (in the QuickPoll Detailed Status Register, bit
17.15), which always shows the setting of an active link.
• Software mode (that is, the HW/SW pin is logic one), the function of bit 0.13 depends on the
Auto-Negotiation Enable bit 0.12. When the Auto-Negotiation sublayer is:
– Enabled, the ICS1893CF isolates bit 0.13 and relies on the results of the auto-negotiation process to
establish the data rate.
– Disabled, bit 0.13 determines the data rate. In this case, setting bit 0.13 to logic:
• Zero selects 10-Mbps ICS1893CF operations.
• One selects 100-Mbps ICS1893CF operations.
7.2.4 Auto-Negotiation Enable (bit 0.12)
This bit provides a means of controlling the ICS1893CF Auto-Negotiation sublayer. Its operation depends
on the HW/SW input pin.
When the ICS1893CF is configured for:
• Hardware mode, (that is, the HW/SW pin is logic zero), the ICS1893CF isolates bit 0.12 and uses the
ANSEL (Auto-Negotiation Select) input pin to determine whether to enable the Auto-Negotiation
sublayer.
Note: In Hardware mode, bit 0.12 is undefined.
• Software mode, (that is, the HW/SW pin is logic one), bit 0.12 determines whether to enable the
Auto-Negotiation sublayer. When bit 0.12 is logic:
– Zero:
• The ICS1893CF disables the Auto-Negotiation sublayer.
• The ICS1893CF bit 0.13 (the Data Rate bit) and bit 0.8 (the Duplex Mode bit) determine the data
rate and the duplex mode.
– One:
• The ICS1893CF enables the Auto-Negotiation sublayer.
• The ICS1893CF isolates bit 0.13 and bit 0.8.
ICS1893CF, Rev. J, 08/11/09
August, 2009
Copyright © 2009, Integrated Device Technology, Inc.
All rights reserved.
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IDT [ INTEGRATED DEVICE TECHNOLOGY ]
