ICS1893CF Data Sheet - Release
Chapter 7 Management Register Set
Chapter 7 Management Register Set
The tables in this chapter detail the functionality of the bits in the management register set. The tables
include the register locations, the bit positions, the bit definitions, the STA Read/Write Access Types, the
default bit values, and any special bit functions or capabilities (such as self-clearing). Following each table
is a description of each bit. This chapter includes the following sections:
• Section 7.1, “Introduction to Management Register Set”
• Section 7.2, “Register 0: Control Register”
• Section 7.3, “Register 1: Status Register”
• Section 7.4, “Register 2: PHY Identifier Register”
• Section 7.5, “Register 3: PHY Identifier Register”
• Section 7.6, “Register 4: Auto-Negotiation Register”
• Section 7.7, “Register 5: Auto-Negotiation Link Partner Ability Register”
• Section 7.8, “Register 6: Auto-Negotiation Expansion Register”
• Section 7.9, “Register 7: Auto-Negotiation Next Page Transmit Register”
• Section 7.10, “Register 8: Auto-Negotiation Next Page Link Partner Ability Register”
• Section 7.11, “Register 16: Extended Control Register”
• Section 7.12, “Register 17: Quick Poll Detailed Status Register”
• Section 7.13, “Register 18: 10Base-T Operations Register”
• Section 7.14, “Register 19: Extended Control Register 2”
ICS1893CF, Rev. J, 08/11/09
August, 2009
Copyright © 2009, Integrated Device Technology, Inc.
All rights reserved.
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