ICS1893CF Data Sheet Rev. J - Release
Chapter 6 Functional Blocks
Upon receiving a valid STA transaction, during a power-on or hardware reset an ICS1893CF compares the
PHYAD field included within the management frame with the value of its PHYAD bits stored in register 16.
(For information on the PHYAD bits, see Table 7-16.) An ICS1893CF responds to all transactions that
match its stored address bits.
6.6.2.5 Management Frame Register Address
A Management Frame includes a 5-bit register address field, REGAD. This field identifies which of the 32
Management Registers are involved in a transaction between an STA and a PHY.
6.6.2.6 Management Frame Operational Code
A management frame includes a 2-bit operational code field, OP. If the operation code is a:
• Read, the REGAD field identifies the register used as the source of data returned to the STA by the
ICS1893CF.
• Write, the REGAD identifies the destination register that is to receive the data sent by the STA to the
ICS1893CF.
6.6.2.7 Management Frame Turnaround
A valid management frame includes a turn-around field (TA), which is a 2-bit time space between the
REGAD field and the Data field. This time allows an ICS1893CF and an STA to avoid contentions during
read transactions. During an operation that is a:
• Read, an ICS1893CF remains in the high-impedance state during the first bit time and subsequently
drives its MDIO pin to logic zero for the second bit time.
• Write, an ICS1893CF waits while the STA transmits a logic one, followed by a logic zero on its MDIO pin.
6.6.2.8 Management Frame Data
A valid management frame includes a 16-bit Data field for exchanging the register contents between the
ICS1893CF and the STA. All Management Registers are 16 bits wide, matching the width of the Data field.
During a transaction that is a:
• Read, (OP is 10b) the ICS1893CF obtains the contents of the register identified in the REGAD field and
returns this Data to the STA synchronously with its MDC signal.
• Write, (OP is 01b) the ICS1893CF stores the value of the Data field in the register identified in the
REGAD field.
If the STA attempts to:
• Read from a non-existent ICS1893CF register, the ICS1893CF returns logic one for all bits in the Data
field, FFFFh.
• Write to a non-existent ICS1893CF register, the ICS1893CF isolates the Data field of the management
frame from every reaching the registers.
Note: The first Data bit transmitted and received is the most-significant bit of a Management Register, bit
X.15.
6.6.2.9 Serial Management Interface Idle State
The MDIO signal is in an idle state during the time between STA transactions. When the Serial
Management Interface is in the idle state, the ICS1893CF disables (that is, tri-states) its MDIO pin, which
enters a high-impedance state. The ISO/IEC 8802-3 standard requires that an MDIO signal be idle for at
least one bit time between management transactions. However, the ICS1893CF does not have this
limitation and can support a continual bit stream on its MDIO signals.
ICS1893CF, Rev. J, 08/11/09
August, 2009
Copyright © 2009, Integrated Device Technology, Inc.
All rights reserved.
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