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1892Y-14 参数 Datasheet PDF下载

1892Y-14图片预览
型号: 1892Y-14
PDF下载: 下载PDF文件 查看货源
内容描述: [Ethernet Transceiver, 1-Trnsvr, CMOS, PQFP64]
分类和应用: 以太网:16GBASE-T电信电信集成电路
文件页数/大小: 148 页 / 1762 K
品牌: IDT [ INTEGRATED DEVICE TECHNOLOGY ]
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ICS1892  
TSD  
10Base-T/100Base-TXIntegrated PHYceiver™  
7.6.2.6 Management Frame Turnaround  
A valid Management Frame includes a turnaround field (TA), which is a 2-bit time space between the  
REGAD field and the Data field. This field requires two bit times and allows the ICS1892 and the STA to  
avoid contentions during read transactions. During an operation that is a:  
Read, the ICS1892 remains in the high-impedance state during the first bit time and subsequently drives  
the MDIO pin to logic zero for the second bit time.  
Write, the ICS1892 waits while the STA transmits a logic one, followed by a logic zero on the MDIO  
signal.  
7.6.2.7 Management Frame Data  
A valid Management Frame includes a 16-bit Data field for exchanging data between the Management  
Registers, and the STA. All Management Registers are 16 bits wide, matching the width of the Data field.  
The first Data bit transmitted and received is the most-significant bit of a Management Register, bit X.15.  
During a transaction that is a:  
Read, OP is 10b and the ICS1892 obtains the value of the register identified in the REGAD field and  
returns the Data to the STA synchronously with the MDC cycles.  
Write, OP is 01b and the ICS1892 stores the value of the Data field in the register identified in the  
REGAD field.  
If the STA attempts to:  
Read from a non-existent ICS1892 register, the ICS1892 returns logic zero for all bits in the Data field.  
Write to a non-existent ICS1892 register, the ICS1892 isolates the Data field.  
7.6.2.8 Idle  
MDIO is idle during the time between STA transactions. During this idle time, the ICS1892 disables its  
tri-state drivers and the MDIO pin enters a high-impedance state. The ISO/IEC 8802-3 standard requires  
that the signal be idle for at least one bit time between management transactions. However, the ICS1892  
does not have this limitation as it can support a continual bit stream on its MDIO.  
IDT™ / ICS™ 10Base-T/100Base-TX Integrated PHYceiver™  
ICS1892  
57  
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