ICS1892
TSD
Chapter 7 Functional Blocks
10Base-T/100BIaCseS-TX1I8nt9eg2rated PHYceiver™
7.6 Functional Block: Management Interface
As part of the MII, the ISO/IEC 8802-3 standard specifies a two-wire serial management interface and
protocol. This interface is used to exchange control, status, and configuration information between the
Station Management entity (STA) and the physical layer device (PHY). For using this management
interface, the ISO/IEC standard specifies the following:
• A set of registers (Section 7.6.1, “Management Register Set Summary”)
• The frame structure (Section 7.6.2, “Management Frame Structure”)
• The protocol
The ICS1892 implementation of the management interface complies fully with the ISO/IEC standard. It
provides a bi-directional data pin (MDIO) along with a clock (MDC) for synchronizing the data transfers.
These pins remain active in all MAC/Repeater Interface modes (that is, the 10/100 MII, 100M Symbol, 10M
Serial, and Link Pulse interface modes).
7.6.1 Management Register Set Summary
The ICS1892 implements a Management Register set that adheres to the ISO/IEC standard. This register
set (discussed in detail in Chapter 8, “Management Register Set”) includes the mandatory ‘Basic’ Control
and Status registers as well as the ICS-specific Extended registers.
7.6.2 Management Frame Structure
The Management Interface is a bi-directional serial interface to exchange configuration, control, and status
data between a PHY such as the ICS1892 and the STA. The PHY and STA exchange data by using the
defined register set. The STA initiates all transactions.
The ISO/IEC specification defines a Management Frame Structure for the serial data stream. The ICS1892
complies with the defined frame structure and protocol. Table 7-2 summarizes the Management Frame
Structure.
Note: The Management Frame Structure starts from and returns to an IDLE condition. However, the
IDLE periods are not part of the Management Frame Structure.
Table 7-2. Management Frame Structure Summary
Frame Field
Frame Function
Data
Comment
Acronym
PRE
Preamble (Bit 1.6)
Start of Frame
Operation Code
PHY Address (Bits 16.10:6)
Register Address
Turnaround
11..11
01
32 ones
2 bits
SFD
OP
10/01 (read/write) 2 bits
PHYAD
REGAD
TA
AAAAA
RRRRR
5 bits
5 bits
Z0/10 (read/write) 2 bits
DDD..DD 16 bits
DATA
Data
ICS1892, Rev. D, 2/26/01
February 26, 2001
© 2000-2001, Integrated Circuit Systems, Inc.
All rights reserved.
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ICS1892
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