ICS1892
10Base-T/100Base-TX Integrated PHYceiver™
TSD
Chapter 7 Functional Blocks
ICS1892 Data Sheet
7.6.2.1 Management Frame Preamble
The ICS1892 continually monitors its management interface for a Management Frame Preamble (PRE),
which indicates the start of an STA transaction. A Management Frame Preamble is a pattern of 32
contiguous logic one bits on the MDIO pin, along with 32 corresponding cycles on the MDC pin.
The ICS1892 supports the Management Frame (MF) Preamble Suppression capability on its Management
Interface, thereby providing a method to shorten the Management Frame and provide an STA with faster
access to the Management Registers. The Management Frame Preamble Suppression bit (bit 1.6 in the
Status Register) indicates whether the ICS1892 can support frames that do not have a preamble.
• The ICS 1890, unlike the ICS1892, does not support MF preamble suppression. Consequently, for the
ICS 1890, bit 1.6 (a Read-Only status bit) is permanently set to logic zero.
• The ICS1892 does support MF preamble suppression. To maintain backward compatibility, the ICS1892
MF Suppression Bit defaults to logic zero after a reset. However, for the ICS1892, this bit is now a
Command Override Write bit instead of a Read-Only bit, thereby providing the STA with the ability to
enable this feature. For an explanation of the Command Override Write bits, see Section 8.1.2,
“Management Register Bit Access”.
7.6.2.2 Management Frame Start
A valid Management Frame includes a start-of-frame delimiter, SFD, immediately following the preamble.
The SFD bit pattern is 01b and is synchronous with two cycles on the MDC pin.
7.6.2.3 Management Frame Operation Code
A valid Management Frame includes an operation code (OP) immediately following the start-of-frame
delimiter. There are two valid operation codes: one for reading from a management register 10b and one
for writing to a management register 01b. The ICS1892 does not respond to the codes 00b and 11b, which
are invalid.
7.6.2.4 Management Frame PHY Address
The ISO/IEC specification is such that a maximum of 32 PHYs can use one set of MDC and MDIO interface
pins. An STA uniquely identifies each of the PHYs sharing a management interface by using the 5-bit PHY
Address field, PHYAD. A valid Management Frame includes a PHYAD field.
Upon receiving a valid STA transaction, the ICS1892 compares the PHYAD included within the frame with
the value of the PHYAD bits stored during a power-on or hardware reset. (For information on the PHYAD
bits, see Table 8-16.) The operation code responds to all transactions that match the internally stored
address bits. The first PHYAD bit transmitted and received is the most-significant bit.
7.6.2.5 Management Frame Register Address
A valid Management Frame includes a 5-bit register address, the REGAD field. This field identifies which of
the 32 Management Registers are to be involved in the transaction. If the operation code is a:
• Read, the REGAD identifies the register used as the source of data returned to the STA by the ICS1892.
• Write, the REGAD identifies the destination register, which is to receive the data sent by the STA to the
ICS1892.
If the STA attempts to:
• Read from a non-existent ICS1892 register, the ICS1892 returns logic zero for all bits in the Data field.
• Write to a non-existent ICS1892 register, the ICS1892 isolates the Data field. The first REGAD bit
transmitted and received is the most-significant bit.
ICS1892, Rev. D, 2/26/01
February 26, 2001
© 2000-2001, Integrated Circuit Systems, Inc.
All rights reserved.
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ICS1892
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