ICS1892
10Base-T/100Base-TX Integrated PHYceiver™
TSD
Chapter 8 Management Register Set
ICS1892 Data Sheet
8.1.2 Management Register Bit Access
The ICS1892 Management Registers include one or more of the three following types of bits:
Table 8-3. Description of Management Register Bit Types
Management
Bit
Description
Register Bit Types Symbol
Read-Only
RO
An STA can obtain the value of a RO register bit. However, it cannot
alter the value of (that is, it cannot write to) an RO register bit. The
ICS1892 isolates any STA attempt to write a value to an RO bit.
Command Override
Write
CW
An STA can read a value from a CW register bit. However, write
operations are conditional, based on the value of the Command
Register Override bit (bit 16.15). When bit 16.15 is logic:
• Zero (the default), the ICS1892 isolates STA attempts to write to
the CW bits (that is, CW bits cannot be altered when bit 16.15 is
logic zero).
• One, the ICS1892 permits an STA to alter the value of the CW bits
in the subsequent register write. (Bit 16.15 is self-clearing and
automatically clears to zero on the subsequent write.)
Read/Write
R/W
An STA can unconditionally read from or write to a R/W register bit.
Read/Write Zero
R/W0
An STA can unconditionally read from a R/W0 register bit, but only a
‘0’ value can be written to this bit.
8.1.3 Management Register Bit Default Values
The tables in this chapter specify for each register bit the default value, if one exists. The ICS1892 sets all
Management Register bits to their default values after a reset. Table 8-4 lists the valid default values for
ICS1892 management register bits.
Table 8-4. Range of Possible Valid Default Values for ICS1892 Register Bits
Default Condition
Default Value
Indicates there is no default value for the bit
–
0
1
Indicates the bit’s default value is logic zero
Indicates the bit’s default value is logic one
State of pin at reset For some bits, the default value depends on the state of a particular pin at reset
(that is, the state value of a pin is latched at reset.) An example of pins that have
a default condition that depends on the state of the pin at reset are the PHY / LED
pins (P0AC, P1CL, P2LI, P3TD, and P4RD) discussed in Section 6.9, “Status
Interface”, Section 8.11, “Register 16: Extended Control Register”, and Section
9.2.2, “Multi-Function (Multiplexed) Pins: PHY Address and LED Pins”
Note: The ICS1892 has a number of reserved bits throughout the Management Registers. Most of these
bits provide enhanced test modes. The Management Register tables provide the default values for
these bits. The STA must not change the value of these bits under any circumstance. If the STA
inadvertently changes the default values of these reserved register bits, normal operation of the
ICS1892 can be affected.
ICS1892, Rev. D, 2/26/01
February 26, 2001
© 2000-2001, Integrated Circuit Systems, Inc.
All rights reserved.
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ICS1892
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