ICS1892
10Base-T/100Base-TX Integrated PHYceiver™
TSD
Chapter 6 Interface Overviews
ICS1892 Data Sheet
6.8 Configuration Interface
The Configuration and Status Interface pins (10/100SEL, 10/LP, ANSEL, DPXSEL, HW/SW, MII/SI,
NOD/REP, RESET* and RXTRI) allow the ICS1892 to be completely configured and controlled in
hardware. With these pins, the ICS1892 can accommodate the following:
• 10M or 100M operations
• 5 MAC/Repeater Interface configurations:
– 10M MII
– 100M MII
– 100M Symbol
– 10M Serial
– Link Pulse
• Node or repeater applications
• Full-duplex or half-duplex data links
In addition to the ISO/IEC-specified, MII control signals, the ICS1892 provides RXTRI, which is a tri-state
enable pin for the MII receive data path. When this pin is active (that is, a logic one), the pins RXCLK,
RXD[3:0], RXER, and RXDV are all tri-stated. Functionally, this pin affects the MII receive channel in the
same way as the Control Register’s isolate bit, bit 0.10. (The isolate bit also affects the transmit data path.)
The ICS1892 can tri-state these seven signals for all five types of MAC/Repeater Interface configurations,
not just the MII interface.
6.9 Status Interface
The ICS1892 LSTA pin provides a Link Status, and the LOCK pin provides a Stream Cipher Locking
Status. In addition, as listed in Table 6-4, the ICS1892 provides the five multiplexed pins that monitor the
data link by providing signals that drive LEDs. (Table 9.2.2 lists the pin numbers.)
Table 6-4. Pins for Monitoring the Data Link
Pin
P0AC
LED Driven by the Pin’s Output Signal
AC (Link Activity) LED
P1CL
P2LI
CL (Collisions) LED
LI (Link Integrity) LED
P3TD
P4RD
TD (Transmit Data) LED
RD (Receive Data) LED
The ICS1892 multiplexes each of these five LED output signals with one of the five PHY address inputs.
The following example shows how this multiplexing takes place:
1. The PHY Address bit P0 and the link activity LED (AC) share pin 58. During a reset of the ICS1892, the
signal on the link activity LED pin (as well as the other four LED pins) become inputs.
2. When the ICS1892 leaves the reset state, it latches the state of these inputs into the PHY Address bits
(that is, the Serial Management Port Address) described in Table 8-16.
3. Next, the ICS1892 converts these pin signals to output signals that can drive an LED directly as
follows: The state/value of each PHY Address bit is selected by connecting its associated LED signal
to either VDD (to select a logic one) or VSS (to select a logic zero).
4. After the reset process completes, the ICS1892 uses the latched PHY address to drive the LED,
independent of its connection to VDD or VSS
.
ICS1892, Rev. D, 2/26/01
February 26, 2001
© 2000-2001, Integrated Circuit Systems, Inc.
All rights reserved.
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IDT™ / ICS™ 10Base-T/100Base-TX Integrated PHYceiver™
ICS1892
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IDT [ INTEGRATED DEVICE TECHNOLOGY ]
