ICS1892
10Base-T/100Base-TX Integrated PHYceiver™
TSD
Chapter 6 Interface Overviews
ICS1892 Data Sheet
6.5 Serial Management Interface
The ISO/IEC 8802-3 standard specifies a two-wire Serial Management Interface and protocol as part of the
MII. This interface is used to exchange configuration, control, and status information between a Station
Management entity (an STA) and a physical layer device (a PHY). The ISO/IEC standard specifies a frame
structure and protocol for this interface as well as a set of Management Registers that it can access. The
ICS1892 implementation of this interface complies fully with the ISO/IEC standard. It provides a
bi-directional data pin (MDIO) along with an input pin for the clock (MDC). The clock is used to synchronize
all data transfers between a PHY and the STA.
In addition to the ISO/IEC defined registers, the ICS1892 provides several extended status and control
registers to provide more refined control of the MII and MDI interfaces. For example, the QuickPoll Detailed
Status Register provides the ability to acquire the most-important status functions with a single MDIO read.
In the ICS1892, the MDIO and MDC pins remain active for all the MAC/Repeater Interface modes, that is,
10M/100M MII, 100M Symbol, 10M Serial, and Link Pulse. Therefore, to the ICS1892 the signals from
these pins represent the Serial Management Interface, not just the MII Management Interface.
6.6 Twisted-Pair Interface
The ICS1892 twisted-pair interface consists of the following:
• Twisted-Pair Transmitter: The differential Twisted-Pair Transmit pins TP_TXP and TP_TXN
• Twisted-Pair Receiver: The differential Twisted-Pair Receive pins TP_RXP and TP_RXN
• Transmit current-select pins: 10TCSR and 100TCSR
The ICS1892 uses the same pins for both 10Base-T and 100Base-TX operating modes. The differential
Twisted-Pair Transmit and Twisted-Pair Receive pins directly interface with a universal magnetic module,
which in turn interfaces with a single RJ-45 connector. The universal magnetic module has two isolation
transformers: one for the transmit channel and one for the receive channel. The isolation transformers
provide the interface between the ICS1892 and the twisted-pair medium.
6.7 Clock Reference Interface
The REF_IN and REF_OUT pins provide the ICS1892 Clock Reference Interface. The ICS1892 requires a
single clock reference with a frequency of 25 MHz 50 parts per million. This accuracy is necessary to meet
the interface requirements of the ISO/IEE 8802-3 standard, specifically clauses 22.2.2.1 and 24.2.3.4.
The ICS1892 supports three clock source configurations. The clock source can be from (1) an oscillator, (2)
a CMOS driver, or (3) a crystal. The following paragraphs offer specific design recommendations for these
clock sources.
6.7.1 Clock Source: Oscillator or CMOS Driver
When using either an oscillator or a CMOS driver, the design must provide a connection from the clock
source to the ICS1892 REF_IN pin while leaving the ICS1892 REF_OUT pin unconnected. ICS also
recommends that the design provide a dedicated driver for the REF_IN pin.
ICS1892, Rev. D, 2/26/01
February 26, 2001
© 2000-2001, Integrated Circuit Systems, Inc.
All rights reserved.
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IDT™ / ICS™ 10Base-T/100Base-TX Integrated PHYceiver™
ICS1892
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IDT [ INTEGRATED DEVICE TECHNOLOGY ]
