ICS1524A
Name:
Register:
Index:
Loop Control Register
1h
Read / Write*
Bit Name Bit # Reset Value Description
PFD0-2
Reserved
PSD 0-1
Reserved
0-2
3
4-5
6 -7
0
0
0
0
Charge Pump Gain
Reserved
Post-Scaler Divider
Reserved
Bit
0-2
Name
PFD0-2
Description
Charge Pump Gain
Bit 2
0
0
0
0
1
1
1
1
Bit 1
0
0
1
1
0
0
1
1
Bit 0
0
1
0
1
0
1
0
1
CP Ga i n ( µ A/ 2
π
r a d )
1
2
4
8
16
32
64
128
3
4-5
Reserved
PSD 0-1
Post-Scaler Divider — Divides the output of the VCO to the DPA and Feedback Divider.
Bit 5
0
0
1
1
Bit 4
0
1
0
1
PSD Divider
2 (default)
4
8
16
6-7
Reserved
*
Double-buffered register. Actual working registers are loaded during software PLL reset.
See register 8h for details.
ICS1524A Rev D 12/23/2005
7