ICS1524A
Detailed Register Description
Name:
Register:
Index:
PDen
PD_Pol
Ref_Pol
Fbk_Pol
Fbk_Sel
Func_Sel
EnPLS
EnDLS
Bit
0
Name
PDen
Input Control
0h
Read / Write
0
1
2
3
4
5
6
7
1
0
0
0
0
0
1
0
Description
Charge Pump Enable
0 = External Enable via PDEN pin
1 = Always Enable
Charge Pump Enable Polarity
0 = Active High
1 = Active Low
External Reference Polarity —
Edge of input signal on which Phase/Frequency Detector triggers.
0 = Rising Edge (default)
1 = Falling Edge
External Reference Feedback Polarity — Edge of EXTFB (pin 6) signal on which
Phase/Frequency Detector triggers when external feedback is used (Reg0 [4]=1).
0 = Positive Edge (default)
1 = Negative Edge
External Feedback Select
0 = Internal Feedback (default)
1 = External Feedback
Function Output Select — Selects re-clocked output to FUNC (pin 15).
0 = Recovered HSYNC (default). Regenerated HSYNC output.
1 = External HSYNC. Schmitt-trigger conditioned input from HSYNC (pin 7).
Enable LOCK/REF (pin14) Output
EnPLS EnDLS IN_SEL
LOCK/REF(14)
0
0
N/A
0
0
1
N/A 1 if DPA locked, 0 otherwise
1
0
N / A 1 i f P L L l o c ke d , 0 o t h e r w i s e
Post Schmitt trigger
1
1
0
HSYNC(7) XOR Ref_Pol
1
1
1
F
osc
÷
Osc_Div
Bit Name Bit # Reset Value Description
Charge Pump Enable
Charge Pump Enable Polarity
External Reference Polarity
External Reference Feedback Polarity
External Feedback Select
Function Output Select
Enable PLL Lock Status Output on LOCK/REF pin
Enable DPA Lock Status Output on LOCK/REF pin
1
PD_Pol
2
Ref_Pol
3
Fbk_Pol
4
Fbk_Sel
5
Func_Sel
6
7
EnPLS
EnDLS
ICS1524A Rev D 12/23/2005
6
IDT [ INTEGRATED DEVICE TECHNOLOGY ]
