ICS1524A
Pin Descriptions
PIN NO.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
P I N NA M E
VDDD
VSSD
S DA
SCL
PDEN
EXTFB
HSYNC
EXTFIL
XFILRET
V D DA
VSSA
OSC
I CADR
LOCK/REF
FUNC
CLK
D PAC L K
VDDQ
VSSQ
D PAC L K –
D PAC L K +
CLK–
CLK+
IREF
2
TYPE
PWR
PWR
IN/OUT
IN
IN
IN
IN
IN
IN
PWR
PWR
IN
IN
SSTL
SSTL
SSTL
SSTL
PWR
PWR
PECL
PECL
PECL
PECL
IN
DESCRIPTION
Digital supply
Digital ground
Serial data
Serial clock
C h a rg e P u m p
External feedback
Horizontal sync
External filter
External filter return
Analog supply
Analog ground
Oscillator
I C address
Lock indicator/reference
Function output
P i xe l c l o c k t
DPA Delayed Clock
Output driver supply
Output driver ground
DPA Delayed PECL clock -
DPA Delayed PECL clock +
PECL clock -
PECL clock +
Reference current
2
COMMENTS
3.3V to digital sections
Ground for digital sections
I
2
C-bus
1
I
2
C-bus
1
S u s p e n d s c h a rg e p u m p
1
External divider input to P F D
1
Clock input to PLL
1
External PLL loop filter
External PLL loop filter return
3.3V for analog circuitry
Ground for analog circuitry
I n p u t f r o m c r y s t a l o s c i l l a t o r p a c k a g e
1, 2
C h i p I
2
C a d d r e s s s e l e c t
Low = 4Dh read, 4Ch write
High = 4Fh read, 4Eh write
Displays PLL or DPA lock or REF input
SSTL_3 selectable HSYNC output
Non-Delayed SSTL_3 Clock
DPA Delayed SSTL_3 Clock
3.3V VDD for output drivers
Ground for output drivers
DPA Delayed Inverted PECL Clock Open drain.
DPA Delayed PECL Clock
Non-Delayed Inverted PECL Clock
Non-Delayed PECL Clock
Reference current for PECL outputs
Open drain.
Open drain.
Open drain.
Notes:
1. These LVTTL inputs are 5 V-tolerant.
2. Connect to ground if unused.
ICS1524A Rev D 12/23/2005
4
IDT [ INTEGRATED DEVICE TECHNOLOGY ]
