IS61C632A
READ CYCLE SWITCHING CHARACTERISTICS (Over Operating Range)
-4
-5
-6
-7
-8
Symbol Parameter
Min. Max.
Min. Max.
Min. Max.
Min. Max.
Min. Max. Unit
tKC
tKH
tKL
Cycle Time
8
—
—
—
4
10
—
—
—
5
12
—
—
—
6
13
—
—
—
7
15
—
—
—
8
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Clock High Time
4
4
4
6
6
Clock Low Time
4
4
4
6
6
tKQ
tKQX
Clock Access Time
—
—
—
2
—
2
—
2
(2)
Clock High to Output Invalid
Clock High to Output Low-Z
Clock High to Output High-Z
Output Enable to Output Valid
Output Disable to Output Invalid
Output Enable to Output Low-Z
Output Disable to Output High-Z
Address Setup Time
1.5
0
—
—
4
1.5
0
—
—
5
—
—
6
—
—
6
—
—
6
(2,3)
tKQLZ
0
0
0
(2,3)
tKQHZ
tOEQ
1.5
—
1.5
—
2
2
2
4
5
—
0
6
—
0
6
—
0
6
(2)
tOEQX
0
—
—
4.5
—
—
—
—
—
—
—
—
—
—
—
0
—
—
4.8
—
—
—
—
—
—
—
—
—
—
—
—
—
6
—
—
6
—
—
6
(2,3)
tOELZ
0
0
0
0
0
(2,3)
tOEHZ
tAS
—
—
—
2.5
2.5
2.5
2.5
2.5
0.5
0.5
0.5
0.5
0.5
45
—
2.5
2.5
2.5
2.5
2.5
0.5
0.5
0.5
0.5
0.5
—
2.5
2.5
2.5
2.5
2.5
0.5
0.5
0.5
0.5
0.5
80
2.5
2.5
2.5
2.5
2.5
0.5
0.5
0.5
0.5
0.5
25
2.5
2.5
2.5
2.5
2.5
0.5
0.5
0.5
0.5
0.5
35
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
tSS
Address Status Setup Time
Write Setup Time
tWS
tCES
tAVS
tAH
Chip Enable Setup Time
Address Advance Setup Time
Address Hold Time
tSH
Address Status Hold Time
Write Hold Time
tWH
tCEH
tAVH
tCFG
Chip Enable Hold Time
Address Advance Hold Time
Configuration Setup(1)
66.7 —
Notes:
1. Configuration signal MODE is static and must not change during normal operation.
2. Guaranteed but not 100% tested. This parameter is periodically sampled.
3. Tested with the load in Figure 2.
8
Integrated Circuit Solution Inc.
SSR001-0B
ICSI [ INTEGRATED CIRCUIT SOLUTION INC ]
