IS61C632A
TRUTH TABLE
OPERATION
ADDRESS
USED
CE1
CE2
CE3 ADSP ADSC ADV WRITE OE
DQ
Deselected, Power-down
Deselected, Power-down
Deselected, Power-down
Deselected, Power-down
Deselected, Power-down
Read Cycle, Begin Burst
Read Cycle, Begin Burst
Write Cycle, Begin Burst
Read Cycle, Begin Burst
Read Cycle, Begin Burst
Read Cycle, Continue Burst
Read Cycle, Continue Burst
Read Cycle, Continue Burst
Read Cycle, Continue Burst
Write Cycle, Continue Burst
Write Cycle, Continue Burst
None
None
None
None
None
External
External
External
External
External
Next
H
L
L
L
L
L
L
L
L
X
L
X
L
X
X
H
X
H
L
L
L
L
L
X
X
X
X
X
X
X
X
X
X
X
X
X
L
L
H
H
L
L
X
X
L
X
X
X
X
X
X
X
X
X
X
L
X
X
X
X
X
X
X
L
H
H
H
H
H
H
L
X
X
X
X
X
L
H
X
L
H
L
H
L
H
X
X
L
H
L
H
X
X
High-Z
High-Z
High-Z
High-Z
High-Z
Q
High-Z
D
Q
High-Z
Q
High-Z
Q
High-Z
D
D
Q
High-Z
Q
High-Z
D
X
H
H
H
H
H
X
X
X
X
X
X
X
X
X
X
X
X
L
X
X
L
L
L
H
H
H
H
H
H
H
H
H
H
H
H
L
H
H
H
H
H
X
X
H
X
H
H
X
X
H
X
L
X
X
H
H
X
H
X
X
H
H
X
H
Next
Next
Next
Next
L
L
L
L
Next
L
L
Read Cycle, Suspend Burst Current
Read Cycle, Suspend Burst Current
Read Cycle, Suspend Burst Current
Read Cycle, Suspend Burst Current
Write Cycle, Suspend Burst Current
Write Cycle, Suspend Burst Current
Notes:
H
H
H
H
H
H
H
H
H
H
L
L
D
1. All inputs except OE must meet setup and hold times for the Low-to-High transition of clock (CLK).
2. Wait states are inserted by suspending burst.
3. X means don't care. WRITE=L means any one or more byte write enable signals (BW1-BW4) and BWE are LOW or GW is
LOW. WRITE=H means all byte write enable signals are HIGH.
4. For a Write operation following a Read operation, OE must be HIGH before the input data required setup time and held HIGH
throughout the input data hold time.
5. ADSP LOW always initiates an internal READ at the Low-to-High edge of clock. A WRITE is performed by setting one or more
byte write enable signals and BWE LOW or GW LOW for the subsequent L-H edge of clock.
PARTIAL TRUTH TABLE
FUNCTION
GW
BWE BW1 BW2 BW3 BW4
READ
READ
WRITE Byte 1
WRITE All Bytes
WRITE All Bytes
H
H
H
X
L
H
X
L
L
X
X
H
L
L
X
X
H
H
L
X
H
H
L
X
H
H
L
X
X
X
4
Integrated Circuit Solution Inc.
SSR001-0B
ICSI [ INTEGRATED CIRCUIT SOLUTION INC ]
