IC61LV256
WRITE CYCLE NO. 2(WE Controlled, OE is HIGH During Write Cycle) (1,2)
t
WC
ADDRESS
OE
VALID ADDRESS
t
HA
LOW
CE
t
AW
t
PWE1
WE
t
SA
t
HZWE
t
LZWE
HIGH-Z
DATA UNDEFINED
DOUT
t
SD
t
HD
DATAIN VALID
DIN
WRITE CYCLE NO. 3(WE Controlled, OE is LOW During Write Cycle) (1)
t
WC
ADDRESS
VALID ADDRESS
t
HA
LOW
LOW
OE
CE
t
t
AW
t
PWE2
WE
t
SA
HZWE
t
LZWE
HIGH-Z
DATA UNDEFINED
DOUT
t
SD
t
HD
DATAIN VALID
DIN
Notes:
1. The internal write time is defined by the overlap of CE LOW and WE LOW. All signals must be in valid states to initiate a Write,
but any one can go inactive to terminate the Write. The Data Input Setup and Hold timing are referenced to the rising or falling
edge of the signal that terminates the Write.
2. I/O will assume the High-Z state if OE > VIH.
8
Integrated Circuit Solution Inc.
AHSR027-0B 11/28/2003
ICSI [ INTEGRATED CIRCUIT SOLUTION INC ]
