IC61LV256
WRITE CYCLE SWITCHING CHARACTERISTICS(1,2) (Over Operating Range)
-8 ns
-10 ns
-12 ns
-15 ns
Symbol Parameter
Min. Max.
Min. Max.
Min. Max.
Min. Max.
Unit
ns
tWC
tSCE
tAW
Write Cycle Time
8
7
7
—
—
—
10
8
—
—
—
12
8
—
—
—
15
10
10
—
—
—
CE to Write End
ns
Address Setup Time
to Write End
8
8
ns
tHA
Address Hold
0
—
0
—
0
—
0
—
ns
from Write End
tSA
tPWE
tSD
tHD
tHZWE
Address Setup Time
0
7
—
—
—
—
3.5
—
0
10
5
—
—
—
—
4
0
12
6
—
—
—
—
6
0
15
7
—
—
—
—
7
ns
ns
ns
ns
ns
ns
(4)
WE Pulse Width
Data Setup to Write End
Data Hold from Write End
WE LOW to High-Z Output
WE HIGH to Low-Z Output
4.5
0
0
0
0
(3)
—
0
—
0
—
0
—
0
(3)
tLZWE
—
—
—
Notes:
1. Test conditions assume signal transition times of 3 ns or less, timing reference levels of 1.5V, input pulse
levels of 0 to 3.0V and output loading specified in Figure 1.
2. The internal write time is defined by the overlap of CE LOW and WE LOW. All signals must be in valid
states to initiate a Write, but any one can go inactive to terminate the Write. The Data Input Setup and Hold
timing are referenced to the rising or falling edge of the signal that terminates the Write.
3. Tested with the load in Figure 2. Transition is measured ±500 mV from steady-state voltage. Not 100%
tested.
4. Tested with OE HIGH.
AC WAVEFORMS
WRITE CYCLE NO. 1(CE Controlled, OE is HIGH or LOW) (1 )
t
WC
VALID ADDRESS
SCE
ADDRESS
CE
t
SA
t
t
HA
t
AW
t
t
PWE1
PWE2
WE
t
HZWE
t
LZWE
HIGH-Z
DATA UNDEFINED
DOUT
t
SD
t
HD
DATAIN VALID
DIN
Integrated Circuit Solution Inc.
7
AHSR027-0B 11/28/2003
ICSI [ INTEGRATED CIRCUIT SOLUTION INC ]
