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IC61LV256-12JG 参数 Datasheet PDF下载

IC61LV256-12JG图片预览
型号: IC61LV256-12JG
PDF下载: 下载PDF文件 查看货源
内容描述: 32K ×8海特高速SRAM与3.3V [32K x 8 Hight Speed SRAM with 3.3V]
分类和应用: 存储内存集成电路静态存储器光电二极管
文件页数/大小: 9 页 / 124 K
品牌: ICSI [ INTEGRATED CIRCUIT SOLUTION INC ]
 浏览型号IC61LV256-12JG的Datasheet PDF文件第1页浏览型号IC61LV256-12JG的Datasheet PDF文件第2页浏览型号IC61LV256-12JG的Datasheet PDF文件第3页浏览型号IC61LV256-12JG的Datasheet PDF文件第4页浏览型号IC61LV256-12JG的Datasheet PDF文件第6页浏览型号IC61LV256-12JG的Datasheet PDF文件第7页浏览型号IC61LV256-12JG的Datasheet PDF文件第8页浏览型号IC61LV256-12JG的Datasheet PDF文件第9页  
IC61LV256  
READ CYCLE SWITCHING CHARACTERISTICS(1) (Over Operating Range)  
-8 ns  
-10 ns  
-12 ns  
-15 ns  
Symbol Parameter  
Min. Max.  
Min. Max.  
Min. Max.  
Min. Max.  
Unit  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
tRC  
Read Cycle Time  
8
2
8
10  
2
10  
10  
5
12  
2
12  
12  
6
15  
2
15  
15  
7
tAA  
Address Access Time  
Output Hold Time  
CE Access Time  
tOHA  
tACE  
tDOE  
tLZOE  
tHZOE  
tLZCE  
tHZCE  
8
0
0
0
0
OE Access Time  
4
(2)  
(2)  
OE to Low-Z Output  
OE to High-Z Output  
CE to Low-Z Output  
CE to High-Z Output  
CE to Power-Up  
4
5
5
6
3
3
3
3
(2)  
4
5
6
7
(2)  
0
0
0
0
(3)  
tPU  
tPD  
8
10  
12  
15  
(4)  
CE to Power-Down  
Notes:  
1. Test conditions assume signal transition times of 3 ns or less, timing reference levels of 1.5V, input pulse  
levels of 0 to 3.0V and output loading specified in Figure 1.  
2. Tested with the load in Figure 2. Transition is measured ±200 mV from steady-state voltage. Not 100%  
tested.  
3. Not 100% tested.  
AC TEST CONDITIONS  
Parameter  
Unit  
0V to 3.0V  
3 ns  
Input Pulse Level  
Input Rise and Fall Times  
Input and Output Timing  
1.5V  
and Reference Levels  
Output Load  
See Figures 1 and 2  
AC TEST LOADS  
319 Ω  
319 Ω  
3.3V  
3.3V  
OUTPUT  
OUTPUT  
353 Ω  
353 Ω  
30 pF  
Including  
jig and  
5 pF  
Including  
jig and  
scope  
scope  
Figure 1.  
Figure 2.  
Integrated Circuit Solution Inc.  
5
AHSR027-0B 11/28/2003