ICS1572
AC Characteristics
SYMBOL
PARAMETER
MIN
20
TYP
20
MAX
160
20
UNITS
MHz
MHz
pF
Fvco
Fxtal
Cpar
Fload
Txhi
VCO Frequency (see Note 1)
Crystal Frequency
5
Crystal Oscillator Loading Capacitance
LOAD Frequency
80
55
MHz
ns
XTAL1 High Time (when driven externally)
XTAL1 Low TIme (when driven externally)
8
8
Txlo
Thigh
ns
Differential Clock Output Duty Cycle
(see Note 2)
45
%
Jclk
Differential Clock Output Cumulative
Jitter (see Note 3)
<0.06
pixel
Tlock
Idd
PLL Acquire Time (to within 1%)
500
15
µs
VDD Supply Current
t.b.d.
t.b.d.
mA
mA
Iddo
VDDO Supply Current (excluding CLK+/-
termination)
20
DIGITAL INPUTS - ICS1572-101
1
2
3
4
5
Address Setup Time
Address Hold Time
Data Setup Time
Data Hold Time
10
10
10
10
ns
ns
ns
ns
ns
STROBE Pulse Width (Thi or Tlo)
20
DIGITAL OUTPUTS - ICS1572-301
6
7
8
DATA/HOLD~Setup Time
DATA/HOLD~Hold Time
10
10
ns
ns
ns
DATCLK Pulse Width (Thi or Tlo)
20
PIPELINE DELAY RESET
9
Reset Activation Time
Reset Duration
2*Tclk
ns
ns
ns
10
11
12
4*Tload
Restart Delay
2*Tload
Restart Matching
-1*Tclk
+1.5*Tclk
ns
DIGITAL OUTPUTS
13
14
CLK+/CLK- Clock Rate
180
+2
MHz
ns
LOAD To LD/N2 Skew (Shift Clock Mode)
-2
0
Note 1: Use of thepost-divider is required for frequencies lower than 20 MHzon CLK+ & CLK- outputs. Useof the post-divider
is recommended for output frequencies lower than 65 MHz.
Note 2: Using load circuit of Figure 6. Duty cycle measured at zero crossings of difference voltage between CLK+ and CLK-.
Note 3: Cumulative jitter is defined as the maximum error (in the time domain) of any CLK edge, at any point in time, compared
with the equivalent edge generated by an ideal frequency source.
ICS laboratory testing indicates that the typical value shown above can be treated as a maximum jitter specification in
virtually all applications. Jitter performance can depend somewhat on circuit board layout, decoupling, and register
programming.
15
ICSI [ INTEGRATED CIRCUIT SOLUTION INC ]
