ICS1531 参数 Datasheet PDF下载

型号：	ICS1531
PDF下载：	下载PDF文件查看货源
内容描述：	888位MSPS A / D转换器与行同步时钟发生器 [Triple 8-bit MSPS A/D Converters with Line-Locked Clock Generator]
分类和应用：	转换器时钟发生器
文件页数/大小：	76 页 / 525 K
品牌：	ICSI [ INTEGRATED CIRCUIT SOLUTION INC ]

ICS1531 Data Sheet - Preliminary

Chapter 3 Pin Diagram and Listings

3.2.3 Pin Listing by Functional Grouping

3.2.3.1 Clock Pins

For more information on the clock pins, see Figure 4-2 and Figure 4-3.)

Table 3-3. Clock Pins

Pin Description

Name

Type

Output ^A•^na^T^lo^hi^g^s^-^p^toⁱⁿ^-D^oⁱ^u^g^tⁱ^p^ta^u^l^ts^C^a^on^ha^v^l^e^f-^r^r^t^a^e^t^r^e^R^p^e^ix^f^e^er^l^e^cⁿ^lo^c^c^e^k^C^fo^l^r^o^l^c^a^k^tc^.^{hing digital output pixel data.}

• ^{Typically, this pin connects to an LCD panel controller/scaler.}

• ^{In this table, see also CLK.}

ADCRCLK

ADCSYNC

CLK

Input or

Output ^A•^na^T^lo^hi^g^s^-^p^toⁱⁿ^-D^pⁱ^r^g^oⁱ^v^tⁱ^a^d^l^e^C^s^o^aⁿ^r^v^e^e^c^r^o^t^v^e^e^r^r^S^ed^yn^H^c^S^.^{YNC signal (that is, an HSYNC signal conditioned by a}

Input or

Schmitt trigger) that aligns to ADCRCLK.

• ^{For some previous ICS chips, the ADCSYNC pin is called FUNC.}

^C•^lo^T^ck^h^.^{is pin outputs the full-rate pixel clock for latching digital output pixel data.}

Output

• ^{In this table, see also ADCRCLK.}

HSYNC

MCLK

Input

Horizontal Sync. (See Table 3-6.)

Output Memory Clock.

• ^{This pin provides an independent user-programmable clock source.}

• ^{Typically, this pin is used by LCD panel controller/scaler chips or microcontrollers.}

^O•^sc^T^il^h^la^is^to^o^r^ut^O^p^u^ut^tp^fr^u^o^t^m^.^{this pin is from a crystal oscillator.}

OSCOUT

Output

• ^{The output frequency is one of the following:}

– The same frequency as the input frequency to the crystal oscillator

– The frequency that results when the input frequency is divided by a programmable

value

^P•^an^T^e^h^l^is^Cl^p^oⁱⁿ^ck^p^.^{rovides an independent user-programmable clock source.}

PNLCLK

REF

• ^{Typically, this pin is used by LCD panel controller/scaler chips or microcontrollers.}

Output Reference.

This pin provides various reference line clock sync signals.

SCL

XIN

Input

Serial Clock. (See Table 3-7.)

Crystal Input.

^T•^his^A^p¹ⁱⁿ^4.^a³^c¹^c⁸^e^1p8^t^-^s^Mⁱⁿ^Hpz^u^c^t^r^f^y^ro^s^{mtalone of the following:}

• ^{An external clock source}

XOUT

Output Crystal Output.

^D•^{o o}^Cⁿ^o^eⁿⁿ^o^e^f^c^th^t^e^it^f^t^ooll^a^ow¹ⁱ⁴ⁿ^.^g³¹^w⁸ⁱ¹^th^8-^th^M^is^H^pzin^cr:ystal.

• ^{Leave it open for an external clock source.}

ICS1531 Rev N 12/1/99

December, 1999

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