AV9110
Output Divider Turth Tables
Table 2
COD1
0
0
1
1
COD0
0
1
0
1
CLK/X
Output Divide
(X)
1
2
4
8
COD1
0
0
1
1
Table 3
COD0
0
1
0
1
VCO
Output Divide
(R)
1
2
4
8
Programming the PLL
The AV9110 has a wide operating range but it is recommended that it is operated within the following limits:
2 MHz < f
REF
< 32 MHz
200 kHz <
f
REF
= Input reference frequency
M = Reference divide, 3 to 127
f
VCO
= VCO output frequency
f
CLK
= CLK or CLK/X output frequency
f
REF
< 5MHz
M
50 MHz < f
VCO
<250 MHz
f
VCO
< 250 MHz
The AV9110 is a classical PLL circuit and the VCO output frequency is given by:
f
VCO
=
N•V• fREF
M
Where N = VCO divided, 3 to 127
M =m Reference divide, 3 to 127
V = Perscale, 1 or 8
The 2 output drivers then give the following frequencies:
f
CLK
=
f
VCO
R
f
CLK/X
=
f
VCO
R•X
= N•V• fREF
MR
=
f
VCLK
X
or f
REF
(output mixable by bit 17)
Where R, X = output dividers 1, 2, 4 or 8
Notes:
1. Output frequency accuracy will depend solely on input reference frequency accuracy.
2. For output frequencies below 125 MHz, it is recommended that the VCO output divide, R, should be 2 or greater. This will
give improved duty cycle.
3. The minimum output frequency step size is approximately 0.2% due to the divider range provided.
5
ICS [ INTEGRATED CIRCUIT SYSTEMS ]
