PRELIMINARY
Integrated
Circuit
Systems, Inc.
ICS853054
4:1, D
IFFERENTIAL
-
TO
-3.3V
OR
2.5V
LVPECL/ECL C
LOCK
M
ULTIPLEXER
Test Conditions
Minimum
Typical
-1.005
-1.78
-1.225
-1.87
800
V
EE
+ 1.2
0
150
-1 0
-150
-0.94
-1.535
Maximum
Units
V
V
V
V
mV
V
µA
µA
µA
T
ABLE
4D. ECL DC C
HARACTERISTICS
,
V
CC
= 0V; V
EE
= -3.465V
TO
-2.375V
Symbol
V
OH
V
OL
V
IH
V
IL
V
PP
V
CMR
I
IH
I
IL
Parameter
Output High Voltage; NOTE 1
Output Low Voltage; NOTE 1
Input High Voltage
Input Low Voltage
Peak-to-Peak Input Voltage
Input High Voltage
Common Mode Range; NOTE 2, 3
Input
PCLK0:PCLK3
High Current nPCLK0:nPCLK3
PCLK0:PCLK3
Input Low
Current
nPCLK0:nPCLK3
NOTE 1: Outputs terminated with 50
Ω
to V
CC
- 2V.
NOTE 2: Common mode voltage is defined as V
IH
.
NOTE 3: For single-ended applications, the maximum input voltage for PCLKx, nPCLKx is V
CC
+ 0.3V.
T
ABLE
5. AC C
HARACTERISTICS
,
V
CC
= 0V; V
EE
= -3.465V
TO
-2.375V
OR
V
CC
= 2.375
TO
3.465V; V
EE
= 0V
Symbol
f
MAX
t
jit
t
PD
t
sk(pp)
t
R
/ t
F
Parameter
Output Frequency
Buffer Additive Phase Jitter, RMS;
refer to Additive Phase Jitter Section
Propagation Delay; NOTE 1
Par t-to-Par t Skew; NOTE 2, 3
Output Rise/Fall Time
Test Conditions
155.52MHz,
12kHz - 20MHz
Minimum
Typical
Maximum
3.2
0.238
465
TBD
Units
GHz
ps
ps
ps
ps
dB
20% to 80%
200
V
IN
1.6V to 2.4V,
MUX
ISOLATION
MUX Isolation
-55
155.52MHz
All parameters measured up to 1.3GHz unless noted otherwise.
NOTE 1: Measured from the differential input crossing point to the differential output crossing point.
NOTE 2: Defined as skew between outputs on different devices operating at the same supply voltages
and with equal load conditions. Using the same type of inputs on each device, the outputs are measured
at the differential cross points.
NOTE 3: This parameter is defined according with JEDEC Standard 65.
853054AG
www.icst.com/products/hiperclocks.html
4
REV. A JANUARY 5, 2006
ICS [ INTEGRATED CIRCUIT SYSTEMS ]
