PRELIMINARY
Integrated
Circuit
Systems, Inc.
ICS853054
4:1, D
IFFERENTIAL
-
TO
-3.3V
OR
2.5V
LVPECL/ECL C
LOCK
M
ULTIPLEXER
drive 50Ω transmission lines. Matched impedance techniques
should be used to maximize operating frequency and mini-
mize signal distortion.
Figures 3A and 3B
show two different
layouts which are recommended only as guidelines. Other
suitable clock layouts may exist and it would be recommended
that the board designers simulate to guarantee compatibility
across all printed circuit and clock component process varia-
tions.
3.3V
T
ERMINATION FOR
3.3V LVPECL O
UTPUTS
The clock layout topology shown below is a typical termi-
nation for LVPECL outputs. The two different layouts men-
tioned are recommended only as guidelines.
FOUT and nFOUT are low impedance follower outputs that
generate ECL/LVPECL compatible outputs. Therefore, termi-
nating resistors (DC current path to ground) or current sources
must be used for functionality. These outputs are designed to
Z
o
= 50Ω
125Ω
FOUT
FIN
125Ω
Z
o
= 50Ω
FOUT
FIN
Z
o
= 50Ω
50Ω
1
Z
((V
OH
+ V
OL
) / (V
CC
– 2)) – 2
o
50Ω
V
CC
- 2V
RTT
Z
o
= 50Ω
84Ω
84Ω
RTT =
F
IGURE
3A. LVPECL O
UTPUT
T
ERMINATION
F
IGURE
3B. LVPECL O
UTPUT
T
ERMINATION
853054AG
www.icst.com/products/hiperclocks.html
9
REV. A JANUARY 5, 2006
ICS [ INTEGRATED CIRCUIT SYSTEMS ]
