PRELIMINARY
Integrated
Circuit
Systems, Inc.
ICS853054
4:1, D
IFFERENTIAL
-
TO
-3.3V
OR
2.5V
LVPECL/ECL C
LOCK
M
ULTIPLEXER
Type
Input
Input
Input
Input
Power
Input
Power
Input
Input
Input
Input
Output
Pulldown
Pullup/Pulldown
Pulldown
Pullup/Pulldown
Pulldown
Pulldown
Pullup/Pulldown
Pulldown
Pullup/Pulldown
Description
Non-inver ting differential LVPECL clock input.
Inver ting differential LVPECL clock input.
V
CC
/2 default when left floating.
Non-inver ting differential LVPECL clock input.
Inver ting differential LVPECL clock input.
V
CC
/2 default when left floating.
Positive supply pins.
Clock select input pins. LVCMOS/LVTTL interface levels.
Negative supply pin.
Non-inver ting differential LVPECL clock input.
Inver ting differential LVPECL clock input.
V
CC
/2 default when left floating.
Non-inver ting differential LVPECL clock input.
Inver ting differential LVPECL clock input.
V
CC
/2 default when left floating.
Differential output pair. LVPECL interface levels.
T
ABLE
1. P
IN
D
ESCRIPTIONS
Number
1
2
3
4
5, 16
6, 7
8, 13
9
10
11
12
14, 15
Name
PCLK0
nPCLK0
PCLK1
nPCLK1
V
CC
SEL0, SEL1
V
EE
PCLK2
nPCLK2
PCLK3
nPCLK3
nQ, Q
NOTE:
Pullup and Pulldown
refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.
T
ABLE
2. P
IN
C
HARACTERISTICS
Symbol
R
PULLDOWN
R
VDD/2
Parameter
Input Pulldown Resistor
Pullup/Pulldown Resistosr
Test Conditions
Minimum Typical
75
50
Maximum
Units
kΩ
kΩ
T
ABLE
3. C
LOCK
I
NPUT
F
UNCTION
T
ABLE
Inputs
SEL1
0
0
1
1
SEL0
0
1
0
1
Outputs
Q/nQ
PCLK0/nPCLK0
PCLK1/nPCLK1
PCLK2/nPCLK2
PCLK3/nPCLK3
853054AG
www.icst.com/products/hiperclocks.html
2
REV. A JANUARY 5, 2006
ICS [ INTEGRATED CIRCUIT SYSTEMS ]
