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X24C02MIG-3.5 参数 Datasheet PDF下载

X24C02MIG-3.5图片预览
型号: X24C02MIG-3.5
PDF下载: 下载PDF文件 查看货源
内容描述: 串行E2PROM [Serial E2PROM]
分类和应用: 内存集成电路光电二极管可编程只读存储器电动程控只读存储器电可擦编程只读存储器时钟
文件页数/大小: 16 页 / 294 K
品牌: ICMIC [ IC MICROSYSTEMS ]
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X24C02  
Current Address Read  
Internally the X24C02 contains an address counter that  
maintains the address of the last word accessed,  
Random Read  
Random read operations allow the master to access any  
memory location in a random manner. Prior to issuing  
incremented by one. Therefore, if the last access (either  
a read or write) was to address n, the next read operation  
the slave address with the R/W bit set to one, the master  
must first perform a “dummy” write operation. The master  
would access data from address n + 1. Upon receipt of the  
slave address with the R/W bit set to one, the  
ter issues the start condition, and the slave address  
followed by the word address it is to read. After the word  
X24C02 issues an acknowledge and transmits the eight bit  
word during the next eight clock cycles. The master  
address acknowledge, the master immediately reissues  
the start condition and the slave address with the R/W bit  
terminates this transmission by issuing a stop condition,  
omitting the ninth clock cycle acknowledge. Refer to  
set to one. This will be followed by an acknowledge from  
the X24C02 and then by the eight bit word. The master  
Figure 7 for the sequence of address, acknowledge and  
data transfer.  
terminates this transmission by issuing a stop condition,  
omitting the ninth clock cycle acknowledge. Refer to  
Figure 8 for the address, acknowledge and data transfer  
sequence.  
Figure 7. Current Address Read  
S
T
A
R
T
S
T
SLAVE  
ADDRESS  
BUS ACTIVITY:  
MASTER  
DATA  
O
P
SDA LINE  
S
P
A
C
K
BUS ACTIVITY:  
X24C02  
3838 FHD F13  
Figure 8. Random Read  
S
S
T
A
R
T
T
A
R
T
S
T
SLAVE  
ADDRESS  
WORD  
ADDRESS n  
SLAVE  
ADDRESS  
BUS ACTIVITY:  
MASTER  
DATA n  
O
P
SDA LINE  
S
S
P
A
C
K
A
C
K
A
C
K
BUS ACTIVITY:  
X24C02  
3838 FHD F14  
7