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X24C02MIG-3.5 参数 Datasheet PDF下载

X24C02MIG-3.5图片预览
型号: X24C02MIG-3.5
PDF下载: 下载PDF文件 查看货源
内容描述: 串行E2PROM [Serial E2PROM]
分类和应用: 内存集成电路光电二极管可编程只读存储器电动程控只读存储器电可擦编程只读存储器时钟
文件页数/大小: 16 页 / 294 K
品牌: ICMIC [ IC MICROSYSTEMS ]
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X24C02  
The data output is sequential, with the data from address  
and followed by the data from n + 1. The address counter  
Sequential Read  
Sequential Read can be initiated as either a current  
address read or random access read. The first word is  
for read operations increments all address bits, allowing the  
entire memory contents to be serially read during  
transmitted as with the other modes, however, the  
master now responds with an acknowledge, indicating it  
one operation. At the end of the address space (address 255),  
the counter “rolls over” to address 0 and the  
requires additional data. The X24C02 continues to output  
data for each acknowledge received. The master  
X24C02 continues to output data for each acknowledge  
received. Refer to Figure 9 for the address, acknowledge  
and data transfer sequence.  
terminates this transmission by issuing a stop condition,  
omitting the ninth clock cycle acknowledge.  
Figure 9. Sequential Read  
S
T
SLAVE  
ADDRESS  
A
C
K
A
C
K
A
C
K
BUS ACTIVITY:  
MASTER  
O
P
SDA LINE  
P
A
C
K
BUS ACTIVITY:  
X24C02  
DATA n  
DATA n+1  
DATA n+2  
DATA n+x  
3838 FHD F15  
Figure 10. Typical System Configuration  
V
CC  
SDA  
SCL  
MASTER  
SLAVE  
SLAVE  
TRANSMITTER/  
RECEIVER  
MASTER  
TRANSMITTER/  
RECEIVER  
MASTER  
TRANSMITTER  
TRANSMITTER/  
RECEIVER  
RECEIVER  
3838 FHD F16  
8