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X24C02MIG-3.5 参数 Datasheet PDF下载

X24C02MIG-3.5图片预览
型号: X24C02MIG-3.5
PDF下载: 下载PDF文件 查看货源
内容描述: 串行E2PROM [Serial E2PROM]
分类和应用: 内存集成电路光电二极管可编程只读存储器电动程控只读存储器电可擦编程只读存储器时钟
文件页数/大小: 16 页 / 294 K
品牌: ICMIC [ IC MICROSYSTEMS ]
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X24C02  
DEVICE ADDRESSING  
Following the start condition, the X24C02 monitors the  
SDA bus comparing the slave address being transmitted  
with its slave address (device type and state of A0, A1 and  
Following a start condition the master must output the  
address of the slave it is accessing. The most significant  
A2 inputs). Upon a correct compare the X24C02 outputs an  
four bits of the slave are the device type identifier  
(see Figure 4). For the X24C02 this is fixed as 1010[B].  
acknowledge on the SDA line. Depending on the state of the  
R/W bit, the X24C02 will execute a read or write operation.  
Figure 4. Slave Address  
WRITE OPERATIONS  
DEVICE TYPE  
IDENTIFIER  
Byte Write  
For a write operation, the X24C02 requires a second  
address field. This address field is the word address,  
1
0
1
0
A2  
A1  
A0 R/W  
comprised of eight bits, providing access to any one of the  
256 words of memory. Upon receipt of the word  
DEVICE  
ADDRESS  
address the X24C02 responds with an acknowledge, and  
awaits the next eight bits of data, again responding  
3838 FHD F09  
with an acknowledge. The master then terminates the  
transfer by generating a stop condition, at which time the  
The next three significant bits address a particular device.  
A system could have up to eight X24C02 devices on the  
bus (see Figure 10). The eight addresses are defined by the  
state of the A0, A1 and A2 inputs.  
X24C02 begins the internal write cycle to the nonvolatile  
memory. While the internal write cycle is in progress the  
X24C02 inputs are disabled, and the device will not  
respond to any requests from the master. Refer to  
The last bit of the slave address defines the operation to be  
performed. When set to one a read operation is  
selected, when set to zero a write operations is selected.  
Figure 5 for the address, acknowledge and data transfer  
sequence.  
Figure 5. Byte Write  
S
T
S
T
SLAVE  
WORD  
ADDRESS  
A
BUS ACTIVITY:  
ADDRESS  
DATA  
R
T
MASTER  
O
P
SDA LINE  
S
P
A
C
K
A
C
K
A
C
K
BUS ACTIVITY:  
X24C02  
3838 FHD F010  
Figure 6. Page Write  
S
T
A
R
T
S
T
SLAVE  
ADDRESS  
WORD  
ADDRESS (n)  
BUS ACTIVITY:  
MASTER  
DATA n  
DATA n+1  
DATA n+3  
O
P
SDA LINE  
S
P
A
C
K
A
C
K
A
C
K
A
C
K
A
C
K
BUS ACTIVITY:  
X24C02  
NOTE: In this example n = xxxx 000 (B); x = 1 or 0  
3838 FHD F011  
5