欢迎访问ic37.com |
会员登录 免费注册
发布采购

X24645PMG 参数 Datasheet PDF下载

X24645PMG图片预览
型号: X24645PMG
PDF下载: 下载PDF文件 查看货源
内容描述: 先进的2线串行E2PROM带座LockTM保护 [Advanced 2-Wire Serial E2PROM with Block LockTM Protection]
分类和应用: 可编程只读存储器
文件页数/大小: 18 页 / 317 K
品牌: ICMIC [ IC MICROSYSTEMS ]
 浏览型号X24645PMG的Datasheet PDF文件第1页浏览型号X24645PMG的Datasheet PDF文件第2页浏览型号X24645PMG的Datasheet PDF文件第3页浏览型号X24645PMG的Datasheet PDF文件第4页浏览型号X24645PMG的Datasheet PDF文件第6页浏览型号X24645PMG的Datasheet PDF文件第7页浏览型号X24645PMG的Datasheet PDF文件第8页浏览型号X24645PMG的Datasheet PDF文件第9页  
X24645  
The last bit of the slave address defines the operation to be  
performed. When set HIGH a read operation is  
selected, when set LOW, a write operation is selected.  
DEVICE ADDRESSING  
Following a start condition the master must output the  
address of the slave it is accessing (see Figure 4). The  
next two bits are the device select bits. A system could have  
up to four X24645’s on the bus. The four  
Following the start condition, the X24645 monitors the SDA  
bus comparing the slave address being transmitted  
with its slave address device type identifier. Upon a  
correct compare the X24645 outputs an acknowledge on  
addresses are defined by the state of the S1 and S2 inputs.  
S2 of the slave address must be the inverse of  
the S2 input pin.  
the SDA line. Depending on the state of the R/W bit, the  
X24645 will execute a read or write operation.  
Figure 4. Slave Address  
WRITE OPERATIONS  
Byte Write  
HIGH ORDER  
ADDRESS  
BITS  
DEVICE  
SELECT  
For a write operation, the X24645 requires a second ad-  
dress field. This address field is the byte address, com-  
prised of eight bits, providing access to any one of 8192  
words in the array. Upon receipt of the byte address, the  
S
2
S
1
A10  
A11  
A12  
A9  
A8 R/W  
X24645 responds with an acknowledge and awaits the  
next eight bits of data, again responding with an acknowledge  
2783 ILL F07.1  
The master then terminates the transfer by generating a  
The next five bits of the slave address are an extension of stop condition, at which time the X24645 begins  
the array’s address and are concatenated with  
the internal write cycle to the nonvolatile memory. While the  
internal write cycle is in progress the X24645 inputs  
the eight bits of address in the byte address field,  
providing direct access to the whole 8192 x 8 array.  
are disabled, and the device will not respond to any requests  
from the master. Refer to Figure 5 for the address,  
acknowledge and data transfer sequence.  
Figure 5. Byte Write  
S
T
S
T
O
P
SLAVE  
ADDRESS  
BYTE  
ADDRESS  
A
R
T
BUS ACTIVITY:  
MASTER  
DATA  
SDA LINE  
S
P
A
C
K
A
C
K
A
C
K
BUS ACTIVITY:  
X24645  
2783 ILL F08.1  
5