X24645
The data output is sequential, with the data from
address n followed by the data from n + 1. The address
Sequential Read
Sequential reads can be initiated as either a current
address read or random access read. The first byte is
counter for read operations increments all address bits,
allowing the entire memory contents to be serially read
transmitted as with the other modes, however, the
master now responds with an acknowledge, indicating
during one operation. At the end of the address space
(address 8191), the counter “rolls over” to 0 and the
it requires additional data. The X24645 continues to
output data for each acknowledge received. The read
X24645 continues to output data for each acknowledge
received. Refer to Figure 9 for the address,
operation is terminated by the master; by not responding
with an acknowledge and then issuing a
stop condition.
acknowledge and data transfer sequence.
Figure 9. Sequential Read
S
SLAVE
ADDRESS
A
C
K
A
C
K
A
C
K
T
O
P
BUS ACTIVITY:
MASTER
SDA LINE
P
A
C
K
BUS ACTIVITY:
X24645
DATA n
DATA n+1
DATA n+2
DATA n+x
2783 ILL F13
Figure 10. Typical System Configuration
V
CC
PULL-UP
RESISTORS
SDA
SCL
MASTER
SLAVE
SLAVE
TRANSMITTER/
RECEIVER
MASTER
TRANSMITTER/
RECEIVER
MASTER
TRANSMITTER
TRANSMITTER/
RECEIVER
RECEIVER
2783 ILL F14
8
ICMIC [ IC MICROSYSTEMS ]
