TM
This X24645 device has been acquired by
IC MICROSYSTEMS from Xicor, Inc.
ICmic
8192 x 8 Bit
IC MICROSYSTEMS
64K
X24645
2
Advanced 2-Wire Serial E PROM with Block LockTM Protection
FEATURES
DESCRIPTION
The X24645 is a CMOS 65,536-bit serial E2PROM,
internally organized 8192 x 8. The X24645 features a
•2.7V to 5.5V Power Supply
•Low Power CMOS
—Active Read Current Less Than 1mA
—Active Write Current Less Than 3mA
serial interface and software protocol allowing operation
on a simple two wire bus.
—Standby Current Less Than 1∝A
•Internally Organized 8192 x 8
•New Programmable Block Lock Protection
—Software Write Protection
—Programmable hardware Write Protect
Two device select inputs (S1, S2) allow up to four
devices to share a common two wire bus.
A Write Protect Register at the highest address location,
1FFFh, provides three new write protection
2
•Block Lock (0, 1/4, 1/2, or all of the E PROM
array)
features: Software Write Protect, Block Write Protect, and
Hardware Write Protect. The Software Write
•2 Wire Serial Interface
Protect feature prevents any nonvolatile writes to the
X24645 until the WEL bit in the write protect register is
•Bidirectional Data Transfer Protocol
•32 Byte Page Write Mode
—Minimizes Total Write Time Per Byte
•Self Timed Write Cycle
—Typical Write Cycle Time of 5ms
•High Reliability
—Endurance: 100,000 Cycles
—Data Retention: 100 Years
•Available Packages
set. The Block Write Protection feature allows the user to
individually write protect four blocks of the array by
programming two bits in the write protect register. The
Programmable Hardware Write Protect feature allows
the user to install the X24645 with WP tied to VCC,
program the entire memory array in place, and then
enable the hardware write protection by programming a
WPEN bit in the write protect register. After this,
—8-Lead PDIP
selected blocks of the array, including the write protect
register itself, are permanently write protected, as long
as WP remains HIGH.
—8-Lead SOIC (JEDEC)
—14-Lead SOIC (JEDEC)
—20-Lead TSSOP
FUNCTIONAL DIAGRAM
WP
H.V. GENERATION
START CYCLE
TIMING &
CONTROL
V
CC
V
SS
WRITE PROTECT
REGISTER AND
SDA
START
STOP
LOGIC
LOGIC
CONTROL
LOGIC
SLAVE ADDRESS
REGISTER
2
E PROM
XDEC
256 X 256
LOAD
WORD
INC
SCL
+COMPARATOR
ADDRESS
COUNTER
S
S
2
1
R/W
YDEC
8
CK
D
OUT
PIN
DATA REGISTER
D
OUT
ACK
2783 ILL F01
Xicor, 1995, 1996 Patents Pending
Characteristics subject to change without notice
2783-3.5 5/13/96 T1/C0/D0 NS
1
ICMIC [ IC MICROSYSTEMS ]
