iC-MSBSAFETY, iC-MSB2
SIN/COS SIGNAL CONDITIONER WITH 1Vpp DRIVER
Rev D2, Page 17/29
TEST MODE
iC-MSB switches to test mode when a voltage greater When test mode is quit with TMODE > 0, then iC-
than VTMon is applied to pin ERR (precondition: MSB again reads out its configuration from the EEP-
TMODE(0) = 1). In response iC-MSB transmits its con- ROM, accessible at the device ID filed to DEVID(6:0)
figuration settings as current-modulated data using er- of adr 0x00. In TMODE = 0x00 the EEPROM is read
ror signal I/O pin ERR either directly from the RAM completely; in all other cases only the address range
(for TMEM = 1) or after re-reading the EEPROM (for 0x00 to 0x21 is read to keep the configuration time
TMEM = 0).
for device testing short. When test mode is quit with
TMODE = 0x00 iC-MSB continues operation without
any interruption.
TMEM
Adr 0x18, bit 7
0
1
EEPROM contents
iC-MSB RAM contents
TMODE
Adr 0x15, bit 7:6
Code
Function during test
mode
Function following test
mode
Table 15: Test Mode Memory Selection
00
01
Normal operation
Normal operation
TMEM = 0:
Repeated read out of
EEPROM
Should the voltage at the ERR pin fall below
VTMoff test mode is terminated and data transmission
aborted.
Transmission of
EEPROM data, address
range 0x1B-0x7F
TMEM = 1:
Transmission of RAM
data, address range
0x3B-0x43
The clock rate for the data output is determined by
ENFAST. Two clock rates can be selected: 780 ns for
ENFAST = 1 or 3.125 µs for ENFAST = 0 (see Electri-
cal Characteristics, D08, for clock frequency and toler-
ances).
10
11
Normal operation
Repeated read out of
EEPROM
Transmission of
Repeated read out of
EEPROM data, address EEPROM
range 0x0-0x7F
Data is output in Manchester code via two clock pulses
per bit. To this end the lowside current source switches
between a Z state (OFF = 0 mA) and an L state (ON =
2 mA).
Table 16: Test Mode Functions
VP
U23-B
VP LM393
VP
7
8
6
5
VP
VP
C21
100nF
C22
100nF
-
The bit information lies in the direction of the current
source switch:
U22-S
AD8029
VN
U23-S
LM393
GND
7
+
4
4
Zero bit: change of state Z → L (OFF to ON)
JP4
R24
470
ERR
One bit: Change of state L → Z (ON to OFF)
max. 5V
VDD
M22
IRLML6401
C24
VP
R26
100pF
100k
R23
2K
C26
100nF
R28
51k
U22-A
U23-A
LM393
R25
2k
2
Transmission consists of a start bit (a one bit), 8 data
bits and a pause interval in Z state (the timing is iden-
tical with an EEPROM access via the I2C interface).
D21
LL4148
-
M21
2N7002
6
2
3
DATA_ON
AD8029
-
3
1
NDIS
DATA_OUT
+
8
+
R21
475k
8
4
R27
100k
U21
LM285
VP
5
C25
100nF
R22
365k
VDD
Example: byte value = 1000 1010
C23
100nF
Transmission including the start bit: 1 1000 1010
In Manchester code: LZ LZZL ZLZL LZZL LZZL
dra_mq1d_error_schem
Figure 1: Example circuit for the decoding and con-
version of the current-modulated signals
to logic levels.
Decoding of the data stream:
ZZZZZZ LZ LZ ZL ZL ZL LZ ZL LZ ZL ZZZZZZ
Pause 1 1 0 0 0 1 0 1 0 Pause
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