iC-MSBSAFETY, iC-MSB2
SIN/COS SIGNAL CONDITIONER WITH 1Vpp DRIVER
Rev D2, Page 14/29
I2C Slave Mode (ENSL = 1)
Register
Read access in I2C slave mode (ENSL = 1)
Content
In this mode iC-MSB behaves like an I2C slave with the
device ID 0x55 and the configuration interface permits
write and read accesses to iC-MSB’s internal registers.
Address
0x00-0x18 Configuration: register addresses 0x00-0x18
0x19-0x1A Not available
0x1B-0x1E OEM data: register addresses 0x1B-0x1E
0x1F
Chip release (ROM)
For chip release verification purposes an identification
value is stored under ROM address 0x1F; a write ac-
cess to this address is not permitted.
0x20-0x23 Configuration: register addresses 0x20-0x23
0x24-0x37 Not available
0x38
Configuration: register address 0x18
0x39-0x3A Not available
CHPREL
Code
0x00
Adr 0x1F, bit 7:0 (ROM)
Chip Release
0x3B-0x3E OEM data: register addresses 0x1B-0x1E
0x3F
Chip release (ROM)
Not available
iC-MSB SAFETY v4
iC-MSB SAFETY v5
iC-MSB2 v5
0x40-0x43 Current error memory
0x44-0x7F Not available
0x04
0x05
0x25
Table 9: RAM Read Access
Table 7: Chip Release
Register
Address
0x00
Write access in I2C slave mode (ENSL = 1)
Access and conditions
NTRI
Code
0
Adr 0x02, bit 7
Changes possible, no restrictions
Function
0x01
Changes possible (wrong entries for CFGIBN can
limit functions)
Output drivers disabled
1
Setting the operating mode, output drivers active
NTRI is evaluated only during I2C slave mode.
0x02
Bit 7 = 0 (NTRI): changes to bits (6:0) permitted
A change of operating mode follows only on writing
Bit 7 = 1 (NTRI); when doing so changes to bits
(6:0) are not permitted.
Notes
Table 8: Tristate Function And Op. Mode Change
0x03-0x16 Changes possible, no restrictions
0x17
Bit 3 = 1 (ENSL):
changes to bits (7:4) and (2:0) permitted
0x18
Changes possible, no restrictions
0x19-0x1A Not available
0x1B-0x1E Changes possible, no restrictions
others
No changes permitted
Table 10: RAM Write Access
ICHAUS [ IC-HAUS GMBH ]
