iC-MR 13-BIT S&H SIN/COS
INTERPOLATOR WITH CONTROLLER INTERFACES
Rev A1, Page 41/44
Status and command register
ADV and error bit ERR_ABS are updated. If the pro-
Read access to the status byte provides the current cess is successful, the cycle counter is set.
system status.
Command 0x03 initiates a software reset which is also
messaged at pin NRES.
ERR and WARN indicate internal errors which are se-
lected using mask registers 0x22 and 0x23. EWKH
and EWKL signal that write protection is active for
memory areas CONF and/or EDS. The BUSY bit
shows that the internal bus is busy, such as when data
is being read out from or written to the EEPROM. Bit
ADV (absolute data valid) indicates that absolute data
has been successfully read out through the absolute
data interface (ADI); bit PDV (position data valid) sig-
nals that position data is valid. If the configuration
register has been successfully CRCed and if absolute
data has been correctly read out through the absolute
data interface (ADI), the INIT bit is also set.
Command 0x04 triggers a CRC of the internal configu-
ration, during which all configuration registers are read
out and verified by the check sum in registers 0x2E-
0x2F. During this process the BUSY bit in the status
byte and the ERR_KNF bit are set in the error byte.
If the process ends successfully, the ERR_KNF bit is
cancelled.
Commands 0x05 and 0x06 simulate errors for the ERR
bit in the status byte, with 0x05 setting the bit and 0x06
disabling it.
STATUS
Bit
Addr. 0x60; bit 7...0
Status message
R
CMD
Code
0x00
0x01
0x02
0x03
0x04
0x05
0x06
Addr. 0x60; bit 7...0
Function
W
INIT
Configuration complete
Request new position data
ERR
Signalizes error as per mask register EMASK
Write current configuration in EEPROM
Readout new data via absolute data interface
Trigger software reset
WARN
EWKH
EWKL
BUSY
ADV
Signalizes warning as per mask register WMASK
Writing memory area CONF permitted
Writing memory area EDS permitted
Internal data bus busy
CRC check of internal configuration
Activate error simulation ERR bit
Deactivate error simulation ERR bit
Absolute data valid
PDV
Position data valid
Note
All bits signal active high.
Table 81: Command register
Table 80: Status byte
Error mask
On write access register 0x60 acts as a command reg-
ister.
Error byte 0x69 (Table 82) signals internal and external
errors.
ERR_EXT is activated by input pin NERR and con-
veys errors which occur in external devices. Error
bits ERR_EXT, ERR_SYN, ERR_TMP, ERR_AMP, and
ERR_RGL are stored and only cancelled if the error
byte is read accessed. This information is stored for
the parallel interface and for the serial interface in SPI
mode. The following errors are reported:
If command 0x00 is written, new position data is re-
quested. As long as this new data is not yet available,
the PDV (position data valid) bit is disabled in the sta-
tus byte.
Command 0x01 writes the current configuration to the
EEPROM. If no EEPROM is connected up on startup,
this commend has no effect. The configuration - up to
and including register 0x2D - and a newly generated
check sum are otherwise written to the EEPROM. For
the duration of the write process the BUSY bit in the
status byte and the ERR_KNF bit (configuration er-
ror) are set in the error byte. If an error occurs, the
ERR_KNF bit is not cancelled at the end of the pro-
cess.
ERROR
Addr. 0x69; bit 7...0
Error message
R
Bit
ERR_EXT Externally signalized error *
ERR_ABS Error in readout of absolute value
ERR_IPO
Fallen below conversion time of interpolator
ERR_KNF Configuration error
ERR_SYN Synchronisation error counter/interpolator *
ERR_TMP Temperature beyond thresholds *
ERR_AMP Amplitude error *
ERR_RGL Beyond control range of transmit current control *
Command 0x02 triggers a new readout of absolute
data through the absolute data interface. Should this
readout not prove successful, it is set to zero for in-
ternal calculation. At the end of the process status bit
Note
*) Stored message, reset after read access
Table 82: Error byte
ICHAUS [ IC-HAUS GMBH ]
