iC-MFN
8-FOLD FAIL-SAFE N-FET DRIVER
Rev A2, Page 3/13
PACKAGES
QFN24 4 mm x 4 mm to JEDEC
PIN CONFIGURATION QFN24
(top view)
24
23
22
21
20
19
PIN FUNCTIONS
No. Name Function
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
OUT1
VB
VBR
EN5
EN10
IN1
IN2
IN3
IN4
IN5
IN6
IN7
IN8
NOK
ENFS
GNDR
GND
OUT8
OUT7
OUT6
OUT5
OUT4
OUT3
OUT2
TP
Output channel 1
Supply Voltage
Supply Voltage (R)
Enable input hi-level = 5V
Enable input hi-level = 10V
Input channel 1
Input channel 2
Input channel 3
Input channel 4
Input channel 5
Input channel 6
Input channel 7
Input channel 8
Output inverted status
Enable input full scale hi-level = VB
Ground (R)
Ground
Output channel 8
Output channel 7
Output channel 6
Output channel 5
Output channel 4
Output channel 3
Output channel 2
TP Thermal-Pad
1
18
2
17
3
16
4
5
MFN
code...
...
15
14
6
13
7
8
9
10
11
12
The
Thermal Pad
is to be connected to a ground plane on the PCB. Connections between GND, GNDR
and the ground plane should be conciled to system FMEA aspects.
ICHAUS [ IC-HAUS GMBH ]
