iC-JX
16-FOLD 24 V HIGH-SIDE DRIVER WITH µC INTERFACE
Rev C1, Page 11/36
OPERATING REQUIREMENTS: Parallel µC Interface
Operating Conditions: VCC = VDD = 3...5.5 V, VBy = 12...36 V, GNDA = GNDD = 0 V, RSET = 10 kΩ ±1 %
Ta = 0...70 °C, CL() = 150 pF, input level lo = 0.8 V, hi = 2.2 V, reference levels according to figure 3
Item Symbol
No.
Parameter
Conditions
Unit
Min.
Max.
Read Cycle
I001 tAR1, tAR2 Setup Time:
see Figure 4
see Figure 4
30
0
ns
ns
ns
ns
ns
NCS, A0...4 set before NRD hi → lo
I002 tRA
I003 tRD
I004 tDF
Hold Time: NCS, A0...4 set before
NRD lo → hi
Wait Time : Data valid after NRD hi → see Figure 4
120
65
lo
Hold Time: Data Bus high impedance see Figure 4
after NRD lo → hi
Required Read Signal Duration at NRD
I005 tRL
50
Write Cycle
I006 tAW1, tAW2 Setup Time: NCS, A0...4 set before
see Figure 4
see Figure 4
see Figure 4
see Figure 4
see Figure 4
30
100
10
ns
ns
ns
ns
ns
NWR lo → hi
I007 tDW
I008 tWA
I009 tWD
I010 tWL
Setup time :
Data valid before NWR lo → hi
Hold time:
NCS, A0...4 stable after NWR lo → hi
Hold time:
10
Data valid after NWR lo → hi
Required Write Signal Duration at
NWR
50
Read/Write Timing
I011 tcyc
Recovery Time between cycles:
NRD lo → hi to NRD hi → lo,
NRD lo → hi to NWR hi → lo,
NWR lo → hi to NWR hi → lo,
NWR lo → hi to NRD hi → lo
see Figure 4
165
ns
t cyc
A(4:0)
NCS
NRD
tRA
tWA
V
2.4V
2.0V
Input/Output
NWR
tDF
valid
t WD
0.8V
0.45V
D(7:0)
valid
tAR1
tAR2
tAW1
tAW2
t
1
tRD
tRL
0
tDW
t WL
Figure 3: Reference levels for displayed
values of time
Figure 4: Read and write cycle for the parallel interface
ICHAUS [ IC-HAUS GMBH ]
