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IC-JRXPLCC44 参数 Datasheet PDF下载

IC-JRXPLCC44图片预览
型号: IC-JRXPLCC44
PDF下载: 下载PDF文件 查看货源
内容描述: ÂμP接口2A ?? 4 24V高侧驱动器 [µP INTERFACE WITH 2×4 24V HIGH-SIDE DRIVERS]
分类和应用: 驱动器
文件页数/大小: 23 页 / 374 K
品牌: ICHAUS [ IC-HAUS GMBH ]
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iC-JRX  
µP INTERFACE WITH 2×4 24V HIGH-SIDE DRIVERS  
Rev A1, Page 21/23  
Low voltage detection  
When the supply voltage at VCC is switched on, the output transistors are only released by the low voltage  
detector after the power-on enable VCCon has been reached. Should the supply voltage drop to VCCoff during  
operation, the I/O stages are disabled, i.e. the output transistors are turned off and the device reset (signal VOK).  
If the supply voltage should then rise to VCCon, iC-JRX is in its reset state.  
Identification of the device  
An identification code has been introduced to enable identification of device iC-JRX. Bit pattern ‘000000’b can  
be read out under address 5.  
Reset  
A reset (RESN= 0) sets the register entries to the reset values given in the tables. The output transistors and the  
current sources in the I/O stages are shutdown and all stages switched to input mode.  
Operation without the BLFQ signal  
Should no clock signal be available at pin BLFQ, iC-JRX can generate the flash pulse internally from the clock  
signal at pin CLK. To this end, NOBLFQ in control word 3 must be set to ‘1’. The flash period is then calculated  
from the clocking pulse at CLK by division by 219.  
Operation without the CLK signal  
iC-JRX is operable without a clocking pulse at the CLK pin. With NOCLK in control word 3 the clocked filtering  
for the I/O signals and overcurrent messaging is deactivated. The device remains fully functional with one  
exception; the PWM cannot be activated, as this is dependent on CLK.  
The same behavior can be obtained by setting BYPH and BYPL in control word 1 together with BYPSCF in  
control word 4; all filters are avoided by way of a bypass circuit. This has one disadvantage, namely that  
interferences in the load lines, for example, can lead to the unwanted display of interrupts.  
Forced shutdown of output stages  
The output stages can be forcibly shutdown at input POE. A ‘1’ enables logic access to the drivers; an ‘0’  
disables this. With this, a processor-independent watchdog can lock the outputs in the event of error, for  
example. An integrated pull-down resistor increases safety.  
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