iC-JRX
µP INTERFACE WITH 2×4 24V HIGH-SIDE DRIVERS
Rev A1, Page 18/23
OPERATING REQUIREMENTS: µP INTERFACE
Operating Cconditions: VCCD, VCCA= 5V ±10%, VB= 19.2..25.2V, GNDA= GNDD= PGND= 0V,
Ta= 0..70EC, CL()= 150pF, input levels lo= 0.45V, hi= 2.4V, see Fig. 3 for reference levels
Item Symbol Parameter
Conditions
Fig.
Unit
Min.
Max.
Data Word Read Timing
I1
tAR1
tAR2
Setup Time:
4
4
4
4
30
10
ns
ns
ns
ns
ns
CSN, A0..4 set before RDN hi6lo
I2 tRA
I3 tRD
I4 tDF
I5 tRL
Hold Time:
CSN, A0..4 stable after RDN lo6hi
Read Data Access Time:
120
65
data valid after RDN hi6lo
Read Data Hold Time:
ports high impedance after RDN lo6hi
Required Read Signal Duration
at RDN
50
Data Word Write Timing
I6
tAW1
tAW2
Setup Time:
4
4
4
4
4
30
100
10
ns
ns
ns
ns
ns
CSN, A0..4 set before WRN hi6lo
I7 tDW
I8 tWA
I9 tWD
I10 tWL
Write Data Setup Time:
data valid before WRN lo6hi
Hold Time:
CSN, A0..4 stable after WRN lo6hi
Write Data Hold Time:
10
data valid after WRN lo6hi
Required Write Signal Duration
at WRN
50
Read/Write Timing
I11 tcyc
Recovery Time between cycles:
4
165
ns
RDN lo6hi to RDN hi6lo,
RDN lo6hi to WRN hi6lo,
WRN lo6hi to WDN hi6lo,
WRN lo6hi to RDN hi6lo
Fig. 3: Reference levels
Fig. 4: Data word read/write timing
ICHAUS [ IC-HAUS GMBH ]
