iC-JRX
µP INTERFACE WITH 2×4 24V HIGH-SIDE DRIVERS
Rev A1, Page 17/23
ELECTRICAL CHARACTERISTICS
Operating Conditions: VCCD= VCCA= 5V ±10%, VB= 19.2..25.2V,
GNDA= GNDD= PGND= 0V, all inputs wired (to hi respectively to lo), Tj= 0..125EC unless otherwise noted.
Item Symbol Parameter
Conditions
Tj
°C
Fig.
Unit
Min.
Typ.
Max.
µP Interface, I/O Logic, Frequency Divider, Interrupt (cont‘d)
710 Vc()hi
711 Vc()lo
ESD Clamp Voltage hi at
Vc()hi= V() -VCCD; D0..7 with
0.4
1.5
V
V
CSN, WRN, RDN, A0..4, RESN, input function, I()= 20mA
CLK, BLFQ, D0..7, INTN
ESD Clamp Voltage lo at
D0..7 with input function,
-1.5
-0.4
CSN, WRN, RDN, A0..4, RESN, I()= -20mA
CLK, BLFQ, D0..7, INTN
Input POE
F01 Vt()hi
F02 Vt()lo
F03 Vt()hys
F04 Rpd()
F05 tw()lo
F06 tsup()
Threshold Voltage hi
Threshold Voltage lo
Hysteresis
Pull-Down Resistor
Disable/Enable Pulse Width
Permissible Interference Pulse
Width
2.2
72
V
V
mV
kΩ
ns
ns
0.8
300
24
Vt()hys= Vt()hi -t()lo
1000
100
5
F07 td(POE- Power Output Switch-off Delay
IOx)
POE: hi6lo until IOx disabled,
ie. V(IOx)< 80% (VB -Vs(IOx)hi),
RL= 240Ω..1kΩ
µs
F08 Vc()hi
ESD Clamp Voltage hi
Vc()hi= V(POE) -VCCA;
I(POE)= 20mA
I(POE)= -20mA
0.8
2
V
V
F09 Vc()lo
ESD Clamp Spannung lo
-1.5
-0.4
Switching Characteristics
801 td()
Permissible Cycle Duration
800
ns
at CLK
802 tw()
803 td()
Permis. Pulse Width lo at CLK
Permissible Cycle Duration
at BLFQ
400
100
ns
ms
804 tw()
Permis. Pulse Width lo at BLFQ
50
ms
ELECTRICAL CHARACTERISTICS: WAVEFORMS
I
IOxpeak
I
IOxmax
IOxdc
t
t
T
τ
Fig. 1: DC load
Fig. 2: Pulse load, pulse duration 2 ms
ICHAUS [ IC-HAUS GMBH ]
