SI4432 参数 Datasheet PDF下载

型号：	SI4432
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Si4430/31/32-B1

3.4. System Timing

The system timing for TX and RX modes is shown in Figures 8 and 9. The figures demonstrate transitioning from

STANDBY mode to TX or RX mode through the built-in sequencer of required steps. The user only needs to

program the desired mode, and the internal sequencer will properly transition the part from its current mode.

The VCO will automatically calibrate at every frequency change or power up. The PLL T0 time is to allow for bias

settling of the VCO. The PLL TS time is for the settling time of the PLL, which has a default setting of 100 µs. The

total time for PLL T0, PLL CAL, and PLL TS under all conditions is 200 µs. Under certain applications, the PLL T0

time and the PLL CAL may be skipped for faster turn-around time. Contact applications support if faster turnaround

time is desired.

XTAL Settling

TX Packet

Time

600us

Figure 8. TX Timing

XTAL Settling

RX Packet

Time

600us

Figure 9. RX Timing

Rev 1.0