Si4430/31/32-B1
3.3. Interrupts
The Si4430/31/32 is capable of generating an interrupt signal when certain events occur. The chip notifies the
microcontroller that an interrupt event has occurred by setting the nIRQ output pin LOW = 0. This interrupt signal
will be generated when any one (or more) of the interrupt events (corresponding to the Interrupt Status bits) shown
below occur. The nIRQ pin will remain low until the microcontroller reads the Interrupt Status Register(s) (Registers
03h–04h) containing the active Interrupt Status bit. The nIRQ output signal will then be reset until the next change
in status is detected. The interrupts must be enabled by the corresponding enable bit in the Interrupt Enable
Registers (Registers 05h–06h). All enabled interrupt bits will be cleared when the microcontroller reads the
interrupt status register. If the interrupt is not enabled when the event occurs it will not trigger the nIRQ pin, but the
status may still be read at anytime in the Interrupt Status registers.
D7
D6
D5
D4
D3
D2
D1
D0
POR Def.
Add R/W Function/Descript
ion
03
04
R
R
Interrupt Status 1
Interrupt Status 2
ifferr
itxffafull
itxffaem
irxffafull iext ipksent ipkvalid icrcerror
irssi iwut ilbd ichiprdy ipor
—
—
iswdet
ipreaval ipreainval
05 R/W Interrupt Enable 1
enfferr entxffafull entxffaem enrxffafull enext enpksent enpkvalid encrcerror
00h
01h
06 R/W Interrupt Enable 2 enswdet enpreaval enpreainval enrssi enwut enlbd enchiprdy enpor
See “AN440: EZRadioPRO Detailed Register Descriptions” for a complete list of interrupts.
Rev 1.0
23
IBM [ IBM ]
